Abstract: A method of making a semiconductor device includes patterning a conductive layer over a substrate to define a conductive pad having a first width. The method includes depositing a passivation layer, wherein the passivation layer directly contacts the conductive pad. The method includes depositing a protective layer over the passivation layer, wherein the protective layer directly contacts the conductive pad. The method includes depositing an under-bump metallization (UBM) layer directly contacting the conductive pad, wherein the UBM layer has a second width greater than the first width. The method includes depositing a mask layer over the UBM layer; and forming an opening in the mask layer wherein the opening has the second width. The method includes forming a conductive pillar in the opening on the UBM layer; and etching the UBM layer using the conductive pillar as a mask, wherein the etched UBM layer has the second width.

Abstract: A pixel circuit and a driving method thereof, and a display device are provided. The pixel circuit includes a driving sub-circuit, a data writing sub-circuit, a first light-emitting control sub-circuit, a second light-emitting control sub-circuit, a compensation sub-circuit, and a first reset sub-circuit, and is configured to generate a driving current to control a light-emitting element to emit light, the first reset sub-circuit comprises a first transistor, the compensation sub-circuit comprises a second transistor, the first transistor and the second transistor are both polysilicon oxide thin film transistors, and an active layer type of the first transistor and an active layer type of the second transistor are different from an active layer type of a transistor comprised in at least one selected from a group consisting of the driving sub-circuit, the data writing sub-circuit, the first light-emitting control sub-circuit, and the second light-emitting control sub-circuit.

Abstract: A forming operation of resistive memory device is provided. The operation includes: applying a pre-forming gate voltage and a pre-forming bit line voltage to a target memory cell; performing a dense switching forming operation, wherein the dense switching forming operation includes alternately performing dense set operations and dense reset operations on the target memory cell, wherein the dense set operation includes applying a dense switching gate voltage and a dense set bit line voltage; and performing a normal set operation on the target memory cell, wherein the normal set operation includes applying a normal set gate voltage and a normal set bit line voltage to the target memory cell, the normal set gate voltage is greater than the pre-forming gate voltage and the dense switching gate voltage, and the normal set bit line voltage is less than the pre-forming bit line voltage and the dense set bit line voltage.

Abstract: The present disclosure provides a semiconductor wafer. The semiconductor wafer includes: a scribe line between a first row of dies and a second row of dies; and a benchmark circuit disposed adjacent to the scribe line and electrically coupled to a first conductive contact and a second conductive contact. The benchmark circuit includes a first device-under-test (DUT); a second DUT; a first switching circuit configured to selectively couple the first DUT and the second DUT to the first conductive contact; and a second switching circuit configured to selectively couple the first DUT and the second DUT to the second conductive contact.

Abstract: A semiconductor device includes a first contact layer, a second contact layer, an active layer, a photonic crystal layer, a passivation layer, a first electrode and a second electrode. The first contact layer has a first surface and a second surface opposite to each other. Microstructures are located on the second surface. The second contact layer is located below the first surface. The active layer is located between the first contact layer and the second contact layer. The photonic crystal layer is located between the active layer and the second contact layer. The passivation layer is located on the second contact layer. The first electrode is located on the passivation layer and is electrically connected the first surface of the first contact layer. The second electrode is located on the passivation layer and is electrically connected to the second contact layer.

Abstract: Provided are a display panel and a display device. The display panel includes: a base substrate; light-emitting elements including groups of light-emitting elements, at least one group of light-emitting elements including first-region light-emitting elements and second-region light-emitting elements; pixel circuits including groups of pixel circuits, at least one group of pixel circuits including first-type pixel circuits and second-type pixel circuits, at least one second-type pixel circuit is connected with at least one second-region light-emitting element through a conductive line, first light-emitting elements are connected with first pixel circuits through first conductive lines, in the at least one group of light-emitting elements and the at least one group of pixel circuits, first pixel circuits connected with first light-emitting elements are closer to the second display region than each of second pixel circuits connected with second light-emitting elements.

Abstract: A certificate requesting method, a certificate issuing method, a certificate system and a computer-readable medium thereof are provided, in which subscriber identity identification information, a private key and a public key certificate bound to a first security chip are converted into a private key bound to a second security chip via an online identity authentication procedure, and the corresponding public key certificate is issued by a certificate authority server, so as to improve the usability, the convenience and the security thereof.

Abstract: Disclosed are an array substrate and a display panel, including: a base substrate; and a wiring layer, an anode layer, and a light-emitting layer which are stacked on the base substrate sequentially, wherein the wiring layer includes a signal wiring, a first wiring and a second wiring, a projection of the first wiring on the base substrate is separated from a projection of the second wiring on the base substrate, the first and second wirings are respectively disposed on two sides of the anode layer below the anode layer, the signal wiring is between the first and second wirings, the projections of the first and second wirings on the base substrate respectively overlap projections of two sides of the anode layer on the base substrate, and a length of the second wiring is less than that of the signal wiring in an extension direction of the signal wiring.

Abstract: A display substrate and a display device. The display substrate includes a display region, a first connecting wire, and a second connecting wire. A first display region includes a first sub-pixel array, including a plurality of light emitting elements arranged in an array, and the plurality of light emitting elements include a first light emitting element and a second light emitting element. The second display region includes a first pixel circuit array, including a plurality of first pixel circuit units, and the plurality of pixel circuit units include a first pixel circuit (D10) and a second pixel circuit. The first connecting wire (151) is connected to the first pixel circuit and the first light emitting element. The second connecting wire is connected to the second pixel circuit and the second light emitting element. The second connecting wire extends in a first direction, the first connecting wire extends in a second direction.

Abstract: A verification device for verifying a design file for digital lithography comprises a memory and a controller. The memory comprises the design file. The controller is configured to access the design file and apply one or more compliance rules to the design file to determine compliance of the design file. The compliance rules comprises at least one of detecting non-orthogonal edges within the design file, detecting non-compliant overlapping structures within the design file, and detecting a non-compliant interaction between a reference layer of the design file and a target layer of the design file. The controller is further configured to verify the design file in response to a comparison of a number of non-orthogonal edges, non-compliant overlapping structures and non-compliant interactions to a threshold.

Abstract: A sight includes a main body, an erecting unit and a compensating mechanism. The compensating mechanism includes a fixing unit, a cover and an switching unit. A compensating mechanism for a sight includes a base unit, a transmission unit, an adjusting cap, a movable unit and a lock unit. The adjusting cap is located in a first position when the adjusting cap is locked by the lock unit. The adjusting cap in the first position can be rotated in a second direction or in a third direction opposite to the second direction when the lock unit is moved in a first direction to release the adjusting cap. The adjusting cap stops in a second position when the adjusting cap is rotated in the third direction so that the movable unit is propped against an end of a groove of the adjusting cap.

Abstract: This invention relates to a latch for selectively binding lower and upper portions of a container. The latch includes a base having a front face, a rear face, a connected end, and a selectively engageable binding end. The rear face further includes an upward hook, a downward hook, and a binding tooth. The latch is characterized in that the upward hook and the downward hook are configured to engage the lower portion of the container and permit both axial and pivotal movement of latch. The axial movement is between an upward position and a low profile position The pivotal movement is about the connected end such that binding end can move between a disengaged and an engaged position.

Abstract: A semiconductor device package is provided. The semiconductor device package includes providing a first substrate, a computing unit and a power module. The first substrate has a first surface and a second surface opposite to the first surface. The computing unit is adjacent to the first surface. The computing unit includes a semiconductor die. The power module is adjacent to the second surface. The power module includes a power element and a passive element. Each of the semiconductor die, the power element, and the passive element is vertically arranged with respect to each other, and the passive elements are assembled between the semiconductor die and the power element.

Abstract: The present disclosure provides an electronic package. The electronic package includes a photonic component including a first input/output (I/O) port and a second I/O port both at a side of the photonic component. The electronic package also includes a connector disposed adjacent to the side of the photonic component and configured to guide a first light carrying medium to be optically coupled with at least one of the first I/O port and second I/O port of the photonic component.

Abstract: The present disclosure discloses a wave-shaped polyurethane high-frequency linear vibrating screen mesh, which solves the problems of unobvious layering and poor screening effect of the existing screen mesh. The wave-shaped polyurethane high-frequency linear vibrating screen mesh comprises a side blind area and a screening area. The screen area is composed of wave-shaped injection molding polyurethane screen pieces. Materials roll forward along the direction of material flow in a wavy manner. Clamping grooves are formed in the blind area, which can be in buckle fit on rail seats of a small beam of a screening machine. The screen gap direction of the screening area is consistent with the direction of the material flow. Through the arrangement of a wave-shaped screen mesh surface, the wave-shaped polyurethane high-frequency linear vibrating screen mesh effectively optimizes the running state of the materials, and promotes effective layering of coarse and fine materials.

Abstract: A three-stage thermal management design of battery module, battery device, and battery system is provided, which not only prevents the battery cells from being impacted by the environment temperature, but also efficiently controls the temperature of the battery cells, such that the battery cells can reach the requirements of temperature equalization and appropriate opening temperature. The thermal management design of the battery module is mainly a design of a battery cell charging and discharging circuit having heat exchange.

Abstract: A dustproof structure of a grinding tool holder, which comprises a shaft portion and a counterweight portion connected to one end of the shaft portion. The counterweight portion comprises an eccentric block connected to the shaft portion, at least one bearing mounted in the eccentric block, a dustproof ring, and a grinding member assembling head assembled with the bearing. The eccentric block is formed with an assembly port for disposing the bearing and the dustproof ring, the dustproof ring is located on a side of the bearing facing the grinding member assembling head, and formed with a first continuous concave-convex structure on a side away from the bearing, the grinding member assembling head is formed with a second continuous concave-convex structure on a side facing the dustproof ring, the first and second continuous concave-convex structures match with each other and define dust blocking dots.

Abstract: A displaying method and apparatus for application performance management are disclosed. The method includes obtaining data from a target application; mapping the data into a plurality of dimensions; displaying a plurality of layers corresponding to the plurality of dimensions; and displaying, based on a dimension associated with an object supported by the target application, a visualized node corresponding to the object at a corresponding layer of the plurality of layers.

Abstract: In some examples, an electronic device comprises a wireless transceiver to transmit a packet and a processor coupled to the wireless transceiver. The processor is to update a running average of a radiation level over a time period. The running average is based on a quantity of packets transmitted by the wireless transceiver during the time period and a radiation level associated with the quantity of packets. The processor is to determine whether the running average exceeds a threshold and to control transmission power for the packet based on the determination and based on a destination of the packet.