Abstract: A video decoder can be configured to determine that a current block in a current picture of the video data is coded in an affine prediction mode; determine one or more control-point motion vectors (CPMVs) for the current block; identify an initial prediction block for the current block in a reference picture using the one or more CPMVs; determine a current template for the current block in the current picture; and determine an initial reference template for the initial prediction block in the reference picture; and perform a motion vector refinement process to determine a modified prediction block based on a comparison of the current template to the initial reference template.

Abstract: An example device for decoding video data includes one or more processors implemented in circuitry and configured to: generate an inter-prediction block for a current block of video data; generate an intra-prediction block for the current block of video data; generate a final prediction block for the current block of video data from the inter-prediction block and the intra-prediction block, including performing each of combined inter/intra prediction (CIIP) mode, overlapped block motion compensation (OBMC), and luma mapping with chroma scaling (LMCS) while generating the final prediction block; and decode the current block of video data using the final prediction block. To generate the final prediction block, the processors may perform LMCS on a first inter-prediction sub-block, combine the LMCS-mapped first inter-prediction sub-block with the intra-prediction block using CIIP, and perform OBMC between the first CIIP prediction block and a second inter-prediction sub-block.

Abstract: STI structures with step height control are produced using a relatively thin nitrogen-containing layer formed over a substrate. The nitrogen-containing layer may consist of SiN and SiON films with a combined thickness of 900 angstroms or less. Trench openings are formed to extend through the nitrogen-containing layer and into the substrate. Chemical vapor deposition is used to form a dielectric such as an oxide within the trench openings and over the top surface of the nitrogen-containing layer. A polishing operation is used to partially polish the CVD dielectric layer leaving a reduced thickness over the nitrogen-containing layer, and then a dry etch is used to remove the dielectric from over the nitrogen-containing layer and uniformly recede the top surface of the dielectric within the trench. Dishing effects are avoided. The nitrogen-containing layer is removed to produce STI structures with step heights of less than 500 angstroms.

Abstract: STI structures with step height control are produced using a relatively thin nitrogen-containing layer formed over a substrate. The nitrogen-containing layer may consist of SiN and SiON films with a combined thickness of 900 angstroms or less. Trench openings are formed to extend through the nitrogen-containing layer and into the substrate. Chemical vapor deposition is used to form a dielectric such as an oxide within the trench openings and over the top surface of the nitrogen-containing layer. A polishing operation is used to partially polish the CVD dielectric layer leaving a reduced thickness over the nitrogen-containing layer, and then a dry etch is used to remove the dielectric from over the nitrogen-containing layer and uniformly recede the top surface of the dielectric within the trench. Dishing effects are avoided. The nitrogen-containing layer is removed to produce STI structures with step heights of less than 500 angstroms.

Abstract: A method for dry etching a feature to control an etching depth using endpoint detection and a sacrificial hardmask including providing a substrate for etching a feature opening into said substrate, said substrate provided with at least a first dielectric layer overlying the substrate; providing at least a second dielectric layer including a sacrificial hardmask at a predetermined thickness over the at least a first dielectric layer; photolithographically patterning and etching in a first dry etching process through a thickness of the at least a second dielectric layer and the at least a first dielectric layer to expose the substrate for dry etching the feature opening; and, dry etching in a second dry etching process the substrate and the sacrificial hardmask layer to endpoint detection of an underlying layer with respect to the sacrificial hardmask layer to thereby etch through a predetermined thickness of the substrate.

Abstract: A method for dry etching a feature to control an etching depth using endpoint detection and a sacrificial hardmask including providing a substrate for etching a feature opening into said substrate, said substrate provided with at least a first dielectric layer overlying the substrate; providing at least a second dielectric layer including a sacrificial hardmask at a predetermined thickness over the at least a first dielectric layer; photolithographically patterning and etching in a first dry etching process through a thickness of the at least a second dielectric layer and the at least a first dielectric layer to expose the substrate for dry etching the feature opening; and, dry etching in a second dry etching process the substrate and the sacrificial hardmask layer to endpoint detection of an underlying layer with respect to the sacrificial hardmask layer to thereby etch through a predetermined thickness of the substrate.

Abstract: A method for forming sidewall spacers with square shoulders on polysilicon gates and the structure formed by the method are disclosed. In the method, a polysilicon gate is first formed on a silicon substrate wherein the gate has a silicon nitride pad on top. A conformal silicon nitride layer is then blanket deposited on top of the structure followed by the deposition of a silicon oxide layer on top of the conformal silicon nitride layer. The silicon oxide layer is then planarized until a top of the conformal silicon nitride layer is exposed. The conformal silicon nitride layer and the silicon nitride pad are then wet etched away to expose the polysilicon gate by using the silicon oxide layer as a mask. After a photoresist layer is coated and etched-back such that only a cavity formed by the silicon oxide layer, the polysilicon gate and the conformal silicon nitride layer is filled with the photoresist, the silicon oxide layer is wet etched away by an etchant such as HF.

Abstract: A method for forming sidewall spacers with square shoulders on polysilicon gates and the structure formed by the method are disclosed. In the method, a polysilicon gate is first formed on a silicon substrate wherein the gate has a silicon nitride pad on top. A conformal silicon nitride layer is then blanket deposited on top of the structure followed by the deposition of a silicon oxide layer on top of the conformal silicon nitride layer. The silicon oxide layer is then planarized until a top of the conformal silicon nitride layer is exposed. The conformal silicon nitride layer and the silicon nitride pad are then wet etched away to expose the polysilicon gate by using the silicon oxide layer as a mask. After a photoresist layer is coated and etched-back such that only a cavity formed by the silicon oxide layer, the polysilicon gate and the conformal silicon nitride layer is filled with the photoresist, the silicon oxide layer is wet etched away by an etchant such as HF.

Abstract: A method of forming a trench power metal-oxide semiconductor (MOS) transistor over a semiconductor substrate is proposed in the present invention. First, a pad oxide layer is formed on said substrate, a masking layer is then formed on the pad oxide layer. Next, the masking layer and the pad oxide layer are defined the trench pattern, and the substrate is etched to form the trench structure. A gate oxide layer is formed on the outer surface of the trench structure. Then, a conducting layer is fill into said trench structure for serving as a gate structure. The doped areas are formed in the substrate to serve as source structures. Next, the sidewall spacers are formed on sidewalls of the masking layer and the pad oxide layer. A field oxide layer is then formed on the conducting layer.