Abstract: A method of forming CMOS transistor is disclosed. A CMOS transistor having a first active area and a second active area is provided. In order to maintain the concentration of the dopants in the second active area, according to the method of the present invention an ion implantation process is performed to form a lightly doped drain (LDD) in the second active area after an epitaxial layer is formed in the first active area. On the other hand, the ion implantation process is performed to form the respective LDD of the first active area and the second active area. After the epitaxial layer in the first active area is formed, another ion implantation process is performed to implant dopants into the LDD of the second active area again.

Abstract: A method of forming CMOS transistor is disclosed. A CMOS transistor having a first active area and a second active area is provided. In order to maintain the concentration of the dopants in the second active area, according to the method of the present invention an ion implantation process is performed to form a lightly doped drain (LDD) in the second active area after an epitaxial layer is formed in the first active area. On the other hand, the ion implantation process is performed to form the respective LDD of the first active area and the second active area. After the epitaxial layer in the first active area is formed, another ion implantation process is performed to implant dopants into the LDD of the second active area again.

Abstract: A method of manufacturing a MOS transistor, in which, a tri-layer photo resist layer is used to form a patterned hard mask layer having a sound shape and a small size, and the patterned hard mask layer is used to form a gate. Thereafter, by forming and defining a cap layer, a recess is formed through etching in the substrate. The patterned hard mask is removed after epitaxial layers are formed in the recesses. Accordingly, a conventional poly bump issue and an STI oxide loss issue leading to contact bridge can be avoided.

Abstract: A method for manufacturing a MOS transistor includes performing a thermal treatment to repair damaged substrate before forming source/drain extension regions, accordingly negative bias temperature instability (NBTI) is reduced. Since the thermal treatment is performed before forming the source/drain extension regions, heat budget for forming the source/drain extension regions and junction depth and junction profile of the source/drain extension would not be affected. Therefore the provided method for manufacturing a MOS transistor is capable of reducing short channel effect and possesses a superior process compatibility.

Abstract: A interconnect structure and the method for fabricating the same is disclosed in this present invention. By employing a metallic compound layer, the adhesion of the cap layer to the metal layer according to this invention can be improved, and metal migration due to thermal stress in the prior art will not occur in the interconnect structure according to this invention. Furthermore, the interconnect structure and the method for manufacturing the same can efficiently keep the interconnect structure from occurring metal migration, thus no voids from thermal stress will be formed in the interconnect structure. Hence, this invention can prevent the interconnect structure from raising the resistance of the interconnect structure by the voids, and efficiently improve the reliability of the interconnect in a semiconductor structure.

Abstract: A interconnect structure and the method for fabricating the same is disclosed in this present invention. By employing a metallic compound layer, the adhesion of the cap layer to the metal layer according to this invention can be improved, and metal migration due to thermal stress in the prior art will not occur in the interconnect structure according to this invention. Furthermore, the interconnect structure and the method for manufacturing the same can efficiently keep the interconnect structure from occurring metal migration, thus no voids from thermal stress will be formed in the interconnect structure. Hence, this invention can prevent the interconnect structure from raising the resistance of the interconnect structure by the voids, and efficiently improve the reliability of the interconnect in a semiconductor structure.

Abstract: A method of manufacturing a metal-oxide-semiconductor field effect (MOSFET) device. A substrate having an isolating structure thereon is provided. A gate dielectric layer and a conductive layer are sequentially formed over the substrate. The conductive layer and the gate dielectric layer are patterned to form a gate structure. A low dielectric constant material spacer is formed on the sidewall of the gate structure. A source drain region is formed in the substrate on each side of the gate structure.

Abstract: A fabrication method for shallow trench isolation is provided. The method includes forming a pad oxide layer on a substrate, followed by forming a mask layer on the pad oxide layer. The mask layer is then patterned. Using the patterned mask as a mask, the pad oxide layer and the substrate are etched to form a trench in the substrate. A tilt-angled fluorine implantation is performed to form a substrate surface with fluorine ions around the top corner of the trench. A thermal oxidation process is further conducted on a surface of the trench to form a thicker liner oxide layer at the top corner of the trench. An insulation layer is then formed on the substrate, filling the trench. The insulation layer above the mask layer is removed followed by removing the mask layer and the pad oxide layer.

Abstract: A method of manufacturing a metal-oxide-semiconductor field effect (MOSFET) device. A substrate having an isolating structure thereon is provided. A gate dielectric layer and a conductive layer are sequentially formed over the substrate. The conductive layer and the gate dielectric layer are patterned to form a gate structure. A low dielectric constant material spacer is formed on the sidewall of the gate structure. A source drain region is formed in the substrate on each side of the gate structure.

Abstract: A method of reducing junction capacitance. In a doped substrate or well, a super steep counter-doped implantation is performed, so as to form a super steep counter-doped region beneath the source/drain region in the substrate. As a consequence, the region near the source/drain region has a reduced doping concentration, and the junction capacitance of the source/drain region is reduced.

Abstract: A method of reducing junction capacitance of a source/drain region. A gate oxide layer is formed on a first conductive type substrate. A polysilicon layer is formed and patterned on the gate. Light second conductive type ions are implanted into the substrate with the polysilicon layer as a mask. An insulation layer is formed to cover a side wall of the polysilicon layer. A first step heavy of ion implantation with second conductive type ions is perform to the substrate using the polysilicon layer and the spacer as mask, so that a heavily doped region is formed. A second step of heavy ion implantation with the second conductive type ions is performed to the substrate using the polysilicon layer and the spacer as masks, so that the heavily doped region is broadened and deepened with a smooth ion distribution profile.

Abstract: The present invention provides a method of forming a Metal Oxide Semiconductor (MOS) transistor on a substrate of a semiconductor wafer. A gate of the MOS transistor is formed on the substrate. A source and a drain of the MOS transistor are then formed in the substrate. An ion implantation process is performed to form a first doped region, a second doped region and a third doped region. The first doped region is positioned under the gate and overlaps with the channel of the MOS transistor. The second doped region is positioned in a predetermined portion of the substrate under the source. The third doped region is positioned in a predetermined portion of the substrate under the drain. The first doped region, the second doped region, the third doped region, the source, and the drain are all of the same type of semiconductor.

Abstract: A method of fabricating a transistor. A gate structure is formed on a substrate. A spacer is formed on a sidewall of the gate structure. A first doping step is performed with the gate structure and the spacer serving as masks to form a source/drain region in the substrate. A silicide layer is formed on the source/drain region. The spacer is removed. A second doping step is performed with the gate structure serving as a mask to form a lightly doped drain region in the substrate.

Abstract: In one embodiment, the present invention is provided for higher BJT gain and more quality device. Providing a substrate incorporating a device, wherein the device is defined MOS region and BJT region. Conductivity-type well region is formed on the substrate, and then a gate oxide layer is formed on the conductivity-type well region of MOS region. Consequently, a polysilicon layer is deposited on the gate oxide layer of MOS region. Using photolithographic and etching process to define a gate, wherein the polysilicon layer is used as the gate of MOS region. Further implanting ions of a first conductive type into the substrate of MOS region. A first dielectric layer is forming on sidewall of the gate, wherein the first dielectric layer is used as a spacer of MOS region. Sequentially, a first photoresist layer is formed over substrate of BJT region to define an emitter of BJT.