Patents by Inventor Yao-Ching Ku

Yao-Ching Ku has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190204730
    Abstract: A method for fabricating a pellicle includes forming a first dielectric layer over a back surface of a substrate. After forming the first dielectric layer, and in some embodiments, a graphene layer is formed over a front surface of the substrate. In some examples, after forming the graphene layer, the first dielectric layer is patterned to form an opening in the first dielectric layer that exposes a portion of the back surface of the substrate. Thereafter, while using the patterned first dielectric layer as a mask, an etching process may be performed to the back surface of the substrate to form a pellicle having a pellicle membrane that includes the graphene layer.
    Type: Application
    Filed: December 20, 2018
    Publication date: July 4, 2019
    Inventors: Yun-Yue LIN, Hsuan-Chen CHEN, Chih-Cheng LIN, Hsin-Chang LEE, Yao-Ching KU, Wei-Jen LO, Anthony YEN, Chin-Hsiang LIN, Mark CHIEN
  • Patent number: 10162258
    Abstract: A method for fabricating a pellicle includes forming a first dielectric layer over a back surface of a substrate. After forming the first dielectric layer, and in some embodiments, a graphene layer is formed over a front surface of the substrate. In some examples, after forming the graphene layer, the first dielectric layer is patterned to form an opening in the first dielectric layer that exposes a portion of the back surface of the substrate. Thereafter, while using the patterned first dielectric layer as a mask, an etching process may be performed to the back surface of the substrate to form a pellicle having a pellicle membrane that includes the graphene layer.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yun-Yue Lin, Hsuan-Chen Chen, Chih-Cheng Lin, Hsin-Chang Lee, Yao-Ching Ku, Wei-Jen Lo, Anthony Yen, Chin-Hsiang Lin, Mark Chien
  • Patent number: 10163738
    Abstract: A partially fabricated semiconductor device includes a semiconductor overlay structure. The semiconductor overlay structure includes a first gate stack structure over the semiconductor substrate, the first gate stack structure being configured as an overlay mark in an overlay region of the semiconductor substrate. The semiconductor overlay structure further includes a doped region in the semiconductor substrate surrounding the first gate stack structure. The doped region has a first dopant concentration greater than or equal to a second dopant concentration next to a second gate stack structure in a device region of the semiconductor substrate.
    Type: Grant
    Filed: December 7, 2016
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsien-Cheng Wang, Ming-Chang Wen, Chun-Kuang Chen, Yao-Ching Ku
  • Publication number: 20180173092
    Abstract: A method for fabricating a pellicle includes forming a first dielectric layer over a back surface of a substrate. After forming the first dielectric layer, and in some embodiments, a graphene layer is formed over a front surface of the substrate. In some examples, after forming the graphene layer, the first dielectric layer is patterned to form an opening in the first dielectric layer that exposes a portion of the back surface of the substrate. Thereafter, while using the patterned first dielectric layer as a mask, an etching process may be performed to the back surface of the substrate to form a pellicle having a pellicle membrane that includes the graphene layer.
    Type: Application
    Filed: December 15, 2016
    Publication date: June 21, 2018
    Inventors: Yun-Yue LIN, Hsuan-Chen CHEN, Chih-Cheng LIN, Hsin-Chang LEE, Yao-Ching KU, Wei-Jen LO, Anthony YEN, Chin-Hsiang LIN, Mark CHIEN
  • Publication number: 20170084506
    Abstract: A partially fabricated semiconductor device includes a semiconductor overlay structure. The semiconductor overlay structure includes a first gate stack structure over the semiconductor substrate, the first gate stack structure being configured as an overlay mark in an overlay region of the semiconductor substrate. The semiconductor overlay structure further includes a doped region in the semiconductor substrate surrounding the first gate stack structure. The doped region has a first dopant concentration greater than or equal to a second dopant concentration next to a second gate stack structure in a device region of the semiconductor substrate.
    Type: Application
    Filed: December 7, 2016
    Publication date: March 23, 2017
    Inventors: Hsien-Cheng WANG, Ming-Chang WEN, Chun-Kuang CHEN, Yao-Ching KU
  • Patent number: 9543406
    Abstract: The overlay mark and method for making the same are described. In one embodiment, a semiconductor overlay structure includes gate stack structures formed on the semiconductor substrate and configured as an overlay mark, and a doped semiconductor substrate disposed on both sides of the gate stack structure that includes at least as much dopant as the semiconductor substrate adjacent to the gate stack structure in a device region. The doped semiconductor substrate is formed by at least three ion implantation steps.
    Type: Grant
    Filed: November 10, 2011
    Date of Patent: January 10, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsien-Cheng Wang, Ming-Chang Wen, Chun-Kuang Chen, Yao-Ching Ku
  • Patent number: 9026957
    Abstract: An embodiment of a feed-forward method of determining a photomask pattern is provided. The method includes providing design data associated with an integrated circuit device. A thickness of a coating layer to be used in fabricating the integrated circuit device is predicted based on the design data. This prediction is used to generate a gradating pattern. A photomask is formed having the gradating pattern.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: May 5, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Chu Liu, Kuei Shun Chen, Chih-Yang Yeh, Te-Chih Huang, Wen-Hao Liu, Ying-Chou Cheng, Boren Luo, Tsong-Hua Ou, Yu-Po Tang, Wen-Chun Huang, Ru-Gun Liu, Shu-Chen Lu, Yu Lun Liu, Yao-Ching Ku, Tsai-Sheng Gau
  • Patent number: 8987008
    Abstract: The present disclosure provides one embodiment of a method for an integrated circuit (IC). The method includes forming a mandrel pattern on a substrate by a first lithography process; forming a first spacer pattern on sidewalls of the mandrel pattern; removing the mandrel pattern; forming a second spacer pattern on sidewalls of the first spacer pattern; removing the first spacer pattern; and etching the substrate using the second spacer pattern as an etch mask.
    Type: Grant
    Filed: August 20, 2013
    Date of Patent: March 24, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Feng Shieh, Ru-Gun Liu, Hung-Chang Hsieh, Tsai-Sheng Gau, Yao-Ching Ku
  • Publication number: 20150056724
    Abstract: The present disclosure provides one embodiment of a method for an integrated circuit (IC). The method includes forming a mandrel pattern on a substrate by a first lithography process; forming a first spacer pattern on sidewalls of the mandrel pattern; removing the mandrel pattern; forming a second spacer pattern on sidewalls of the first spacer pattern; removing the first spacer pattern; and etching the substrate using the second spacer pattern as an etch mask.
    Type: Application
    Filed: August 20, 2013
    Publication date: February 26, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Feng Shieh, Ru-Gun Liu, Hung-Chang Hsieh, Tsai-Sheng Gau, Yao-Ching Ku
  • Publication number: 20140170537
    Abstract: An embodiment of a feed-forward method of determining a photomask pattern is provided. The method includes providing design data associated with an integrated circuit device. A thickness of a coating layer to be used in fabricating the integrated circuit device is predicted based on the design data. This prediction is used to generate a gradating pattern. A photomask is formed having the gradating pattern.
    Type: Application
    Filed: February 25, 2014
    Publication date: June 19, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: George Liu, Kuei Shun Chen, Chih-Yang Yeh, Te-Chih Huang, Wen-Hao Liu, Ying-Chou Cheng, Boren Luo, Tsong-Hua Ou, Yu-Po Tang, Wen-Chun Huang, Ru-Gun Liu, Shu-Chen Lu, Yu Lun Liu, Yao-Ching Ku, Tsai-Sheng Gau
  • Patent number: 8673520
    Abstract: An intensity selective exposure photomask, also describes as a gradated photomask, is provided. The photomask includes a first region including a first array of sub-resolution features. The first region blocks a first percentage of the incident radiation. The photomask also includes a second region including a second array of sub-resolution features. The second region blocks a second percentage of the incident radiation different that the first percentage. Each of the features of the first and second array includes an opening disposed in an area of attenuating material.
    Type: Grant
    Filed: March 11, 2011
    Date of Patent: March 18, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: George Liu, Kuei Shun Chen, Chih-Yang Yeh, Te-Chih Huang, Wen-Hao Liu, Ying-Chou Cheng, Boren Luo, Tsong-Hua Ou, Yu-Po Tang, Wen-Chun Huang, Ru-Gun Liu, Shu-Chen Lu, Yu Lun Liu, Yao-Ching Ku, Tsai-Sheng Gau
  • Patent number: 8609545
    Abstract: A method and system for fabricating a substrate is disclosed. First, a plurality of process chambers are provided, at least one of the plurality of process chambers adapted to receive at least one plasma filtering plate and at least one of the plurality of process chambers containing a plasma filtering plate library. A plasma filtering plate is selected and removed from the plasma filtering plate library. Then, the plasma filtering plate is inserted into at least one of the plurality of process chambers adapted to receive at least one plasma filtering plate. Subsequently, an etching process is performed in the substrate.
    Type: Grant
    Filed: February 14, 2008
    Date of Patent: December 17, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: I-Hsiung Huang, Chi-Lin Lu, Heng-Jen Lee, Sheng-Chi Chin, Yao-Ching Ku
  • Patent number: 8431291
    Abstract: An intensity selective exposure photomask, also describes as a gradated photomask, is provided. The photomask includes a first region including a first array of sub-resolution features. The first region blocks a first percentage of the incident radiation. The photomask also includes a second region including a second array of sub-resolution features. The second region blocks a second percentage of the incident radiation different that the first percentage.
    Type: Grant
    Filed: October 25, 2011
    Date of Patent: April 30, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: George Liu, Kuei Shun Chen, Chih-Yang Yeh, Te-Chih Huang, Wen-Hao Liu, Ying-Chou Cheng, Boren Luo, Tsong-Hua Ou, Yu-Po Tang, Wen-Chun Huang, Ru-Gun Liu, Shu-Chen Lu, Yu Lun Liu, Yao-Ching Ku, Tsai-Sheng Gau
  • Patent number: 8375347
    Abstract: A method of designing an integrated circuit (“IC”) is provided that includes placing an IC design, where the IC design includes a first element, a second element, and a path coupling the first and second elements, and routing the IC design. Further, the method includes obtaining at least one of resistivity data and capacitance data related to the path, and obtaining timing data related to the path. The method also includes using at least one of the resistivity data, the capacitance data, and the timing data to determine a critical dimension (“CD”) bias to be applied to the path, and modifying the IC design, where modifying includes applying the CD bias to the path.
    Type: Grant
    Filed: May 12, 2009
    Date of Patent: February 12, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Louis Chao-Chiuan Liu, Lee-Chung Lu, Yao-Ching Ku
  • Patent number: 8352888
    Abstract: Methods and systems for providing processing parameters in a secure format are disclosed. In one aspect, a method for providing semiconductor fabrication processing parameters to a design facility is disclosed. The method comprises providing a set of processing parameters of a fabrication facility; creating a model from the set of processing parameters; converting the model into a corresponding set of kernels; converting the set of kernels into a corresponding set of matrices; and communicating the set of matrices to the design facility. In another aspect, a method for providing semiconductor fabrication processing parameters is disclosed. The method comprises providing a set of processing parameters of a fabrication facility; creating a processing model from the set of processing parameters; encrypting the processing model into a format for use with a plurality of EDA tools; and communicating the encrypted processing model format to a design facility.
    Type: Grant
    Filed: May 26, 2011
    Date of Patent: January 8, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ru-Gun Liu, Chih-Ming Lai, Wen-Chun Huang, Boren Luo, I-Chang Shin, Yao-Ching Ku, Cliff Hou
  • Patent number: 8214772
    Abstract: Methods and systems for providing processing parameters in a secure format are disclosed. In one aspect, a method for providing semiconductor fabrication processing parameters to a design facility is disclosed. The method comprises providing a set of processing parameters of a fabrication facility; creating a model from the set of processing parameters; converting the model into a corresponding set of kernels; converting the set of kernels into a corresponding set of matrices; and communicating the set of matrices to the design facility. In another aspect, a method for providing semiconductor fabrication processing parameters is disclosed. The method comprises providing a set of processing parameters of a fabrication facility; creating a processing model from the set of processing parameters; encrypting the processing model into a format for use with a plurality of EDA tools; and communicating the encrypted processing model format to a design facility.
    Type: Grant
    Filed: May 26, 2011
    Date of Patent: July 3, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ru-Gun Liu, Chih-Ming Lai, Wen-Chun Huang, Boren Luo, I-Chang Shin, Yao-Ching Ku, Cliff Hou
  • Publication number: 20120146159
    Abstract: The overlay mark and method for making the same are described. In one embodiment, a semiconductor overlay structure includes gate stack structures formed on the semiconductor substrate and configured as an overlay mark, and a doped semiconductor substrate disposed on both sides of the gate stack structure that includes at least as much dopant as the semiconductor substrate adjacent to the gate stack structure in a device region. The doped semiconductor substrate is formed by at least three ion implantation steps.
    Type: Application
    Filed: November 10, 2011
    Publication date: June 14, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsien-Cheng WANG, Ming-Chang WEN, Chun-Kuang CHEN, Yao-Ching KU
  • Patent number: 8201111
    Abstract: Disclosed is a system and method for integrated circuit designs and post layout analysis. The integrated circuit design method includes providing a plurality of IC devices with various design dimensions; collecting electrical performance data of the IC devices; extracting equivalent dimensions of the IC devices; generating a shape related model to relate the equivalent dimensions to the electrical performance data of the IC devices; and creating a data refinement table using the equivalent dimensions and the electrical performance data.
    Type: Grant
    Filed: August 2, 2011
    Date of Patent: June 12, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Chin Hou, Ying-Chou Cheng, Ru-Gun Liu, Chih-Ming Lai, Yi-Kan Cheng, Chung-Kai Lin, Hsiao-Shu Chao, Ping-Heng Yeh, Min-Hong Wu, Yao-Ching Ku, Tsong-Hua Ou
  • Publication number: 20120040278
    Abstract: An intensity selective exposure photomask, also describes as a gradated photomask, is provided. The photomask includes a first region including a first array of sub-resolution features. The first region blocks a first percentage of the incident radiation. The photomask also includes a second region including a second array of sub-resolution features. The second region blocks a second percentage of the incident radiation different that the first percentage.
    Type: Application
    Filed: October 25, 2011
    Publication date: February 16, 2012
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd., ("TSMC")
    Inventors: George Liu, Kuei Shun Chen, Chih-Yang Yeh, Te-Chih Huang, Wen-Hao Liu, Ying-Chou Cheng, Boren Luo, Tsong-Hua Ou, Yu-Po Tang, Wen-Chun Huang, Ru-Gun Liu, Shu-Chen Lu, Yu Lun Liu, Yao-Ching Ku, Tsai-Sheng Gau
  • Publication number: 20110289466
    Abstract: Disclosed is a system and method for integrated circuit designs and post layout analysis. The integrated circuit design method includes providing a plurality of IC devices with various design dimensions; collecting electrical performance data of the IC devices; extracting equivalent dimensions of the IC devices; generating a shape related model to relate the equivalent dimensions to the electrical performance data of the IC devices; and creating a data refinement table using the equivalent dimensions and the electrical performance data.
    Type: Application
    Filed: August 2, 2011
    Publication date: November 24, 2011
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yung-Chin Hou, Ying-Chou Cheng, Ru-Gun Liu, Chih-Ming Lai, Yi-Kan Cheng, Chung-Kai Lin, Hsiao-Shu Chao, Ping-Heng Yeh, Min-Hong Wu, Yao-Ching Ku, Tsong-Hua Ou