Patents by Inventor Yao-Chun Cheng

Yao-Chun Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11931187
    Abstract: A method for predicting clinical severity of a neurological disorder includes steps of: a) identifying, according to a magnetic resonance imaging (MRI) image of a brain, brain image regions each of which contains a respective portion of diffusion index values of a diffusion index, which results from image processing performed on the MRI image; b) for one of the brain image regions, calculating a characteristic parameter based on the respective portion of the diffusion index values; and c) calculating a severity score that represents the clinical severity of the neurological disorder of the brain based on the characteristic parameter of the one of the brain image regions via a prediction model associated with the neurological disorder.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: March 19, 2024
    Assignees: Chang Gung Medical Foundation Chang Gung Memorial Hospital at Keelung, Chang Gung Memorial Hospital, Linkou, Chang Gung University
    Inventors: Jiun-Jie Wang, Yi-Hsin Weng, Shu-Hang Ng, Jur-Shan Cheng, Yi-Ming Wu, Yao-Liang Chen, Wey-Yil Lin, Chin-Song Lu, Wen-Chuin Hsu, Chia-Ling Chen, Yi-Chun Chen, Sung-Han Lin, Chih-Chien Tsai
  • Publication number: 20240071998
    Abstract: A method of packaging a semiconductor includes: positioning first and second semiconductor dies by one another on a carrier substrate, wherein first and second zones zone are defined with respect to the first die and third and fourth zones are defined with respect to the second die; forming first vias in the first zone, the first vias having a first size; forming second vias in the second zone, the second vias having a second size different from the first; forming third vias in the third zone, the third vias having a third size; forming fourth vias in the fourth zone, the fourth vias having a fourth size different from the third; and electrically connecting the first and second dies with an interconnection die such that electrical signals are exchangeable therebetween.
    Type: Application
    Filed: August 23, 2022
    Publication date: February 29, 2024
    Inventors: Li-Hsien Huang, Hsueh-Lung Cheng, Yao-Chun Chuang, Yinlung Lu
  • Patent number: 8898517
    Abstract: An apparatus for handling a failed processor of a multiprocessor system including at least two processors interconnected by processor interconnects for facilitating transactions of the processors. The at least two processors include a first processor set as a default boot processor in response to a boot up operation of the multiprocessor computer, and a second processor. The apparatus includes: a baseboard management module for detecting and receiving health information of the processors; a multiplexer coupled to the baseboard management module and respectively to the processors, the multiplexer being operative to switch between the processors; and a processor ID controller coupled to the baseboard management module and respectively to the processors. In response to the health information indicating the first processor has failed, the processor ID controller sets the second processor as the default boot processor and the baseboard management module enables the multiplexer to switch to the second processor.
    Type: Grant
    Filed: December 2, 2011
    Date of Patent: November 25, 2014
    Assignee: International Business Machines Corporation
    Inventors: Yao-Chun Cheng, Yuan-Ning Lien, Chuan Yung Liu, Feng-I Liu, Kuei Huang Liu, Michael J. Peters
  • Patent number: 8892944
    Abstract: A method for handling a failed processor of a multiprocessor system, the multiprocessor system comprising at least two processors interconnected by processor interconnects for transactions between processors, the processors comprising a first processor and a second processor, the first processor being set as a default boot processor in response to a boot-up operation of the multiprocessor system. The method comprises: detecting and receiving, via a baseboard management module, health information of the at least two processors; providing a multiplexer operative to switch between the at least two processors, the multiplexer being coupled to the baseboard management module and respectively to the at least two processors; and, in response to the health information indicating the first processor has failed, setting, via a processor ID controller, the second processor as the default boot processor and enabling, via the baseboard management module, the multiplexer to switch to the second processor.
    Type: Grant
    Filed: July 3, 2012
    Date of Patent: November 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Yao-Chun Cheng, Yuan-Ning Lien, Chuan Yung Liu, Feng-I Liu, Kuei Huang Liu, Michael J. Peters
  • Patent number: 8812831
    Abstract: A fan control method for an information handling system is provided. The information handling system includes a device area and a fan for providing air flow to the device area. A plurality of devices is installed on the device area. The method includes the steps of: collecting thermal data of installed devices in the device area when booting up the information handling system; determining a threshold power of the installed devices and a discreteness level of the installed devices based on the thermal data; adjusting an initial speed of the fan based on the discreteness level; and calibrating the speed of the fan to obtain an optimized speed thereof based on the threshold power and the adjusted initial speed. A fan control apparatus for an information handling system is further provided.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: August 19, 2014
    Assignee: International Business Machines Corporation
    Inventors: Yao-Chun Cheng, Edward Y. Kung, Terrence Lee, Kuei H. Liu, Ming-Hui Pan
  • Publication number: 20120278653
    Abstract: A method for handling a failed processor of a multiprocessor system, the multiprocessor system comprising at least two processors interconnected by processor interconnects for transactions between processors, the processors comprising a first processor and a second processor, the first processor being set as a default boot processor in response to a boot-up operation of the multiprocessor system. The method comprises: detecting and receiving, via a baseboard management module, health information of the at least two processors; providing a multiplexer operative to switch between the at least two processors, the multiplexer being coupled to the baseboard management module and respectively to the at least two processors; and, in response to the health information indicating the first processor has failed, setting, via a processor ID controller, the second processor as the default boot processor and enabling, via the baseboard management module, the multiplexer to switch to the second processor.
    Type: Application
    Filed: July 3, 2012
    Publication date: November 1, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Yao-Chun Cheng, Yuan-Ning Lien, Chuan Yung Liu, Feng-I Liu, Kuei Huang Liu, Michael J. Peters
  • Publication number: 20120173922
    Abstract: An apparatus for handling a failed processor of a multiprocessor system including at least two processors interconnected by processor interconnects for facilitating transactions of the processors. The at least two processors include a first processor set as a default boot processor in response to a boot up operation of the multiprocessor computer, and a second processor. The apparatus includes: a baseboard management module for detecting and receiving health information of the processors; a multiplexer coupled to the baseboard management module and respectively to the processors, the multiplexer being operative to switch between the processors; and a processor ID controller coupled to the baseboard management module and respectively to the processors. In response to the health information indicating the first processor has failed, the processor ID controller sets the second processor as the default boot processor and the baseboard management module enables the multiplexer to switch to the second processor.
    Type: Application
    Filed: December 2, 2011
    Publication date: July 5, 2012
    Applicant: International Business Machiness Corporation
    Inventors: Yao-Chun Cheng, Yuan-Ning Lien, Chuan Yung Liu, Feng-I Liu, Kuei Huang Liu, Michael J. Peters
  • Publication number: 20120084551
    Abstract: A fan control method for an information handling system is provided. The information handling system includes a device area and a fan for providing air flow to the device area. A plurality of devices is installed on the device area. The method includes the steps of: collecting thermal data of installed devices in the device area when booting up the information handling system; determining a threshold power of the installed devices and a discreteness level of the installed devices based on the thermal data; adjusting an initial speed of the fan based on the discreteness level; and calibrating the speed of the fan to obtain an optimized speed thereof based on the threshold power and the adjusted initial speed. A fan control apparatus for an information handling system is further provided.
    Type: Application
    Filed: September 30, 2011
    Publication date: April 5, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Yao-Chun Cheng, Edward Y. Kung, Terrence Lee, Kuei H. Liu, Ming-Hui Pan