Abstract: A package structure includes a package substrate, an interposer module, a package lid, and a heat dissipation structure between the interposer module and the package lid, including a thermal interface material (TIM) layer, and a metal barrier layer between the TIM layer and at least one of the interposer module or the package lid, and configured to inhibit formation of an intermetallic compound (IMC) layer. A method of making the package structure includes forming a metal barrier layer comprising Cu (111) on at least one of an interposer module or a package lid, attaching the interposer module, forming a thermal interface material (TIM) layer over the interposer module, and attaching the package lid to the package substrate so that the interposer module, the TIM layer and the metal barrier layer are disposed between the package lid and the package substrate, and the metal barrier layer contacts the TIM layer.

Abstract: A package structure includes a package substrate, a chip on the package substrate, a package lid on the chip, and a structure between the chip and the package lid. The structure may include a thermal interface material (TIM) layer, and a metal layer between the TIM layer and at least one of the chip or the package lid and configured to inhibit formation of an intermetallic compound (IMC) layer. A method of making the package structure includes forming a metal layer including a high-texture structure on at least one of a chip or a package lid, attaching the chip to a package substrate, forming a thermal interface material (TIM) layer over the chip, and attaching the package lid to the package substrate over the chip so that the chip, the TIM layer and the metal layer are disposed between the package lid and the package substrate.

Abstract: A passive device of a semiconductor substrate and method of making same. The passive device includes first and second top metal components on a substrate core having an insulator substrate. A passivation layer is formed over the top metal components and insulator substrate. A first conductive component is formed on the passivation layer electrically contacting the first top metal component, as well as a second conductive component that is formed on the passivation layer and electrically contacts the second top metal component. In addition, the device includes an insulator material that is formed over the first conductive component and the second conductive component. A cavity is defined by the insulator material between the first conductive component and the second conductive component. The device further includes an ABF plug component that is formed in the cavity between the first conductive component and the second conductive component.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a metal line over a first substrate, a second substrate over the metal line, and a through-via penetrating through the second substrate and landing on the metal line. The through-via includes a copper fill having at least 85% (111) crystal orientation. The through-via includes a top portion with a first top width over a bottom portion with a second top width that is smaller than the first top width, and the top portion includes a first bulk portion over a first footing feature. The first bulk portion has first sidewalls, the first footing feature has second sidewalls, and the second sidewalls slant inwards from the first sidewalls to narrow the through-via from the first top width of the top portion to the second top width of the bottom portion.

Abstract: One aspect of the present disclosure pertains to an IC packaging structure that includes a bottom circuit structure having first semiconductor devices on a first substrate, a first interconnect structure over the first semiconductor devices, and a first bonding structure over the first interconnect structure; and a top circuit structure having second semiconductor devices on a second substrate, a second interconnect structure underlying the second semiconductor devices, and a second bonding structure underlying the second interconnect structure. The first bonding structure includes a first metal feature having a first crystalline bulk layer of a metal and a first amorphous surface layer of the metal. The second bonding structure includes a second metal feature having a second crystalline bulk layer of the metal and a second amorphous surface layer of the metal. The top circuit structure is bonded to the bottom circuit structure through the first and second amorphous surface layers.

Abstract: Methods for improving joinder between a surface-mount package and a printed circuit board are disclosed. The warpage at a corner of the surface-mount package and at a corresponding corner of a joint area on the printed circuit board are measured to determine the degree of mismatch. A mini-pad is applied to the corner between the surface-mount package and the joint area on the printed circuit board. The thickness of the mini-pad pushes against the surface-mount package and the printed circuit board, reducing the degree of mismatch below a critical dimension of a ball grid array of the surface-mount package. The surface-mount package can then be soldered to the joint area, reducing or preventing the formation of solder bridges and short circuits.

Abstract: A method of manufacturing a semiconductor package includes forming an under-bump metallization, and forming a redistribution layer. The redistribution layer includes a plurality of metallization layers embedded in intermetal dielectric material. The metallization layers of the redistribution layer electrically connect a semiconductor die with the under-bump metallization. The under-bump metallization includes a bonding pad and a guard ring encircling the bonding pad. The guard ring forms an annular pocket encircling the bonding pad. The annular pocket is filled with a polymer material. A crack formed in underfill material coating a bonding bump bonded to the bonding pad is blocked from penetrating into the redistribution layer using the guard ring.

Abstract: A metal-insulator-metal (MIM) structure and methods of forming the same for reducing the accumulation of external stress at the corners of the conductor layers are disclosed herein. An exemplary device includes a substrate that includes an active semiconductor device. A stack of dielectric layers is disposed over the substrate. A lower contact is disposed over the stack of dielectric layers. A passivation layer is disposed over the lower contact. A MIM structure is disposed over the passivation layer, the MIM structure including a first conductor layer, a second conductor layer disposed over the first conductor layer, and a third conductor layer disposed over the second conductor layer. A first insulator layer is disposed between the first conductor layer and the second conductor layer. A second insulator layer is disposed between the second conductor layer and the third conductor layer. One or more corners of the third conductor layer are rounded.

Abstract: Integrated circuit (IC) structures and methods for forming the same are provided. An IC structure according to the present disclosure includes a substrate, an interconnect structure over the substrate, a guard ring structure disposed in the interconnect structure, a via structure vertically extending through the guard ring structure, and a top metal feature disposed directly over and in contact with the guard ring structure and the via structure. The guard ring structure includes a plurality of guard ring layers. Each of the plurality of guard ring layers includes a lower portion and an upper portion disposed over the lower portion. Sidewalls of the lower portions and upper portions of the plurality of guard ring layers facing toward the via structure are substantially vertically aligned to form a smooth inner surface of the guard ring structure.

Abstract: A semiconductor device with a multi-tier construction includes a first tier having a first die, a second die spaced apart from the first die in a first direction and a fill material therebetween. A second tier overlays the first tier, and includes a bridge die partially overlaying the fill material and the first and second dies. The bridge die provides an electrical interconnection between the first and second dies in the first tier. The device also has a first protective structure aligned with a first interface between an end of the first die and the fill material that includes a first part formed on a first side of the first die at the end of the first die; and a second part formed on a first side of the bridge die. The first and second parts are aligned and form the first protective structure, mitigating cracking near the bridge die.

Abstract: A chip-on-wafer-on-substrate (CoWoS) semiconductor assembly is formed which includes a chip-on-wafer (CoW) sub-assembly of integrated circuit (IC) dies mounted on an interposer, which is in turn mounted on a package substrate with a top metallization stack and a bottom metallization stack using bonding bumps connecting the backside of the interposer and the front side of the package substrate. The bonding bumps provide electrical connections between the ends of through-vias exposed at the backside of the interposer and the top metallization stack of the package substrate. The likelihood of certain failure mechanisms that can adversely affect CoWoS yield are reduced or eliminated by ensuring a total metal thickness of the top metallization stack is greater than a total metal thickness of the bottom metallization stack, but not so much greater as to induce cracking of the underfill material during curing thereof.

Abstract: A method comprises depositing a protection layer over a first substrate, wherein the first substrate is part of a first semiconductor die, forming an under bump metallization structure over the protection layer, forming a connector over the under bump metallization structure, forming a first dummy plane along a first edge of a top surface of the first semiconductor die and forming a second dummy plane along a second edge of the top surface of the first semiconductor die, wherein the first dummy plane and the second dummy plane form an L-shaped region.

Abstract: A semiconductor article which includes a semiconductor substrate, a back end of the line (BEOL) wiring portion on the semiconductor substrate, a through silicon via and a guard ring. The semiconductor substrate is made of a semiconductor material. The BEOL wiring portion includes a plurality of wiring layers having electrically conductive wiring and electrical insulating material. The through silicon via provides a conductive path through the BEOL wiring portion and the semiconductor substrate. The guard ring surrounds the through silicon via in the BEOL wiring portion and in some embodiments in the semiconductor substrate.

Abstract: A semiconductor article which includes a semiconductor substrate, a back end of the line (BEOL) wiring portion on the semiconductor substrate, a through silicon via and a guard ring. The semiconductor substrate is made of a semiconductor material. The BEOL wiring portion includes a plurality of wiring layers having electrically conductive wiring and electrical insulating material. The through silicon via provides a conductive path through the BEOL wiring portion and the semiconductor substrate. The guard ring surrounds the through silicon via in the BEOL wiring portion and in some embodiments in the semiconductor substrate.

Abstract: An organic interposer includes interconnect-level dielectric material layers embedding redistribution interconnect structures, package-side bump structures located on a first side of the interconnect-level dielectric material layers, at least one dielectric capping layer located on a second side of the interconnect-level dielectric material layers, a bonding-level dielectric layer located on the at least one dielectric capping layer, metallic pad structures including pad via portions embedded in the at least one dielectric capping layer and pad plate portions embedded in the bonding-level dielectric layer, and an edge seal ring structure vertically extending from a first horizontal plane including bonding surfaces of the package-side bump structures to a second horizontal plane including distal planar surfaces of the metallic pad structures.

Abstract: A metal-insulator-metal (MIM) structure and methods of forming the same for reducing the accumulation of external stress at the corners of the conductor layers are disclosed herein. An exemplary device includes a substrate that includes an active semiconductor device. A stack of dielectric layers is disposed over the substrate. A lower contact is disposed over the stack of dielectric layers. A passivation layer is disposed over the lower contact. A MIM structure is disposed over the passivation layer, the MIM structure including a first conductor layer, a second conductor layer disposed over the first conductor layer, and a third conductor layer disposed over the second conductor layer. A first insulator layer is disposed between the first conductor layer and the second conductor layer. A second insulator layer is disposed between the second conductor layer and the third conductor layer. One or more corners of the third conductor layer are rounded.

Abstract: A method of fabricating a semiconductor device that includes a first die component and at least one second die component. The first die component includes a substrate, a dielectric layer on the substrate, and one or more metal pads positioned on the dielectric layer. The first die component further includes a passivation/bond film layer that is formed over the one or more metal pads, and one or more bond pad vias that extend through the passivation/bond film layer and contact one or more metal pads. The at least one second die component is bonded to the first die component and includes a substrate, and one or more through silicon vias, with the one or more through silicon vias contacting the one or more bond pad vias.

Abstract: A chip-on-wafer-on-substrate (CoWoS) semiconductor assembly is formed which includes a chip-on-wafer (CoW) sub-assembly of integrated circuit (IC) dies mounted on an interposer, which is in turn mounted on a package substrate with a top metallization stack and a bottom metallization stack using bonding bumps connecting the backside of the interposer and the front side of the package substrate. The bonding bumps provide electrical connections between the ends of through-vias exposed at the backside of the interposer and the top metallization stack of the package substrate. The likelihood of certain failure mechanisms that can adversely affect CoWoS yield are reduced or eliminated by ensuring a total metal thickness of the top metallization stack is greater than a total metal thickness of the bottom metallization stack, but not so much greater as to induce cracking of the underfill material during curing thereof.

Abstract: In an embodiment, a method includes attaching a first package component to a first carrier, the first package component comprising: an aluminum pad disposed adjacent to a substrate; a sacrificial pad disposed adjacent to the substrate, the sacrificial pad comprising a major surface opposite the substrate, a protrusion of the sacrificial pad extending from the major surface; and a dielectric bond layer disposed around the aluminum pad and the sacrificial pad; attaching a second carrier to the first package component and the first carrier, the first package component being interposed between the first carrier and the second carrier; removing the first carrier; planarizing the dielectric bond layer to comprise a top surface being coplanar with the protrusion; and etching a portion of the protrusion.

Abstract: A substrate or IC chip is connected with a second substrate or IC chip. This entails disposing electrically conductive balls on electrical bonding pads of a surface of the substrate or IC chip to form a ball grid array (BGA) disposed on the surface of the substrate or IC chip, and electrically and mechanically connecting the surface of the substrate or IC chip to the second substrate or IC chip using the BGA. An underfill material may be disposed on the surface of the substrate or IC chip around bonds between the balls and the electrical bonding pads. There may be at least two different types of electrically conductive balls in the BGA, such as solder balls and copper-based balls.