Abstract: Embodiments of the present disclosure relate to methods of fabricating conductive features to prevent metal extrusion. Particularly, the conductive feature includes a control layer to reduce grain size of a metal containing layer, thus obtaining a robust structure to decrease extrusion defects. In some embodiments, the control layer is formed between a barrier layer and the conductive feature. In some embodiments, the control layer is formed by adding a control element, such as oxygen, to an upper portion of the barrier layer.

Abstract: A semiconductor device includes a first interlayer dielectric (ILD) layer disposed over a substrate, a control layer disposed over the first ILD layer and containing silicon and oxygen, and a resistor wire disposed over the control layer. An oxygen concentration of the control layer is greater than an oxygen concentration of the first ILD layer.

Abstract: A semiconductor electrochemical plating (ECP) tool includes: a plating cell which receives an ECP solution therein; a support onto which a semiconductor substrate is selectively secured, the support being controllable to selectively dip the semiconductor substrate into ECP solution contained in the plating cell; a recirculation system including a reservoir that receives an overflow of ECP solution from the plating cell, the ECP solution being recirculated from the reservoir back to the plating cell; a bubble monitoring system that detects gas bubbles within the ECP solution; and a degassing system that inhibits at least one of gas bubble formation, nucleation and growth within the ECP solution, wherein the degassing system is controlled at least in part based upon gas bubble detection by the bubble monitoring system.

Abstract: Some implementations described herein provide techniques and apparatuses for forming a copper structure adjacent to a multi-layer film structure included in a semiconductor device. The techniques include using an electroplating process to form the copper structure adjacent to the multi-layer film structure, wherein a pre-layer of chlorine molecules coats a seed layer of the multi-layer film structure during the electroplating process. During formation of the copper structure, a chlorine-enriched interface region (e.g., a control layer including a copper chelate material with chlorine) may be formed between the copper structure and the multi-layer film structure including the seed layer. The chlorine-enriched interface region may reduce a likelihood of electromigration and/or stress migration within the semiconductor device.

Abstract: A method of fabricating a semiconductor device includes forming a first film having a first film stress type and a first film stress intensity over a substrate and forming a second film having a second film stress type and a second film stress intensity over the first film. The second film stress type is different than the first film stress type. The second film stress intensity is about same as the first film stress intensity. The second film compensates stress induced effect of non-flatness of the substrate by the first film.

Abstract: A method of fabricating a semiconductor device includes forming a first film having a first film stress type and a first film stress intensity over a substrate and forming a second film having a second film stress type and a second film stress intensity over the first film. The second film stress type is different than the first film stress type. The second film stress intensity is about same as the first film stress intensity. The second film compensates stress induced effect of non-flatness of the substrate by the first film.

Abstract: A buffer layer may be included between a first conductive electrode layer and an insulator layer, and/or between a second conductive electrode layer and the insulator layer of a capacitor structure to reduce lattice mismatching in the capacitor structure. The buffer layer(s) include a combination of materials that promote lattice matching between the insulator layer and one or more of the conductive electrode layers. This reduces the likelihood of formation of structural defects in the capacitor structure relative to another capacitor structure that does not include the buffer layers.

Abstract: A method of forming a semiconductor device, comprising: forming a first conductive layer on an active device of a substrate; forming a dielectric layer on the first conductive layer; forming a through hole passing through the dielectric layer to expose a portion of the first conductive layer; conformally depositing a glue layer in the through hole to cover the portion of the first conductive layer comprising: forming a plurality of isolated lattices in an amorphous region at which the isolated lattices are uniformly distributed and extend from a top surface of the glue layer and terminate prior to reach a bottom of the glue layer, wherein the glue layer has a predetermined thickness; depositing a conductive material on the glue layer within the through hole, thereby forming a contact via; and forming a second conductive layer on the contact via over the first conductive layer.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes: a substrate; a transistor on the substrate; a first dielectric layer over the transistor; a second dielectric layer over the first dielectric layer; a barrier layer extending from the second dielectric layer to the first dielectric layer; and a conductive structure separated from the second dielectric layer and the first dielectric layer by the barrier layer. The barrier layer includes: a first layer, including titanium or tantalum along inner sidewalls of the first dielectric layer and the second dielectric layer; a second layer, being an oxide of titanium or tantalum and over the first layer; and a third layer, including cobalt and over the second layer.

Abstract: Embodiments of the present disclosure relate to methods of fabricating conductive features to prevent metal extrusion. Particularly, the conductive feature includes a control layer to reduce grain size of a metal containing layer, thus obtaining a robust structure to decrease extrusion defects. In some embodiments, the control layer is formed between a barrier layer and the conductive feature. In some embodiments, the control layer is formed by adding a control element, such as oxygen, to an upper portion of the barrier layer.

Abstract: A semiconductor device includes a first interlayer dielectric (ILD) layer disposed over a substrate, a control layer disposed over the first ILD layer and containing silicon and oxygen, and a resistor wire disposed over the control layer. An oxygen concentration of the control layer is greater than an oxygen concentration of the first ILD layer.

Abstract: A method for performing an electrochemical plating (ECP) process includes contacting a surface of a substrate with a plating solution comprising ions of a metal to be deposited, electroplating the metal on the surface of the substrate, in situ monitoring a plating current flowing through the plating solution between an anode and the substrate immersed in the plating solution as the ECP process continues, and adjusting a composition of the plating solution in response to the plating current being below a critical plating current such that voids formed in a subset of conductive lines having a highest line-end density among a plurality of conductive lines for a metallization layer over the substrate are prevented.

Abstract: A method of fabricating a semiconductor device includes forming a first film having a first film stress type and a first film stress intensity over a substrate and forming a second film having a second film stress type and a second film stress intensity over the first film. The second film stress type is different than the first film stress type. The second film stress intensity is about same as the first film stress intensity. The second film compensates stress induced effect of non-flatness of the substrate by the first film.

Abstract: A method of forming a deep trench isolation in a radiation sensing substrate includes: forming a trench in the radiation sensing substrate; forming a corrosion resistive layer in the trench, in which the corrosion resistive layer includes titanium carbon nitride having a chemical formula of TiCxN(2-x), and x is in a range of 0.1 to 0.9; and filling a reflective material in the trench and over the corrosion resistive layer.

Abstract: Some embodiments of the present disclosure provide a back side illuminated (BSI) image sensor. The back side illuminated (BSI) image sensor includes a semiconductive substrate and an interlayer dielectric (ILD) layer at a front side of the semiconductive substrate. The ILD layer includes a dielectric layer over the semiconductive substrate and a contact partially buried inside the semiconductive substrate. The contact includes a silicide layer including a predetermined thickness proximately in a range from about 600 angstroms to about 1200 angstroms.

Abstract: A method of forming a deep trench isolation in a radiation sensing substrate includes: forming a trench in the radiation sensing substrate; forming a corrosion resistive layer in the trench, in which the corrosion resistive layer includes titanium carbon nitride having a chemical formula of TiCxN(2-x), and x is in a range of 0.1 to 0.9; and filling a reflective material in the trench and over the corrosion resistive layer.

Abstract: A method of fabricating a semiconductor device includes forming a first film having a first film stress type and a first film stress intensity over a substrate and forming a second film having a second film stress type and a second film stress intensity over the first film. The second film stress type is different than the first film stress type. The second film stress intensity is about same as the first film stress intensity. The second film compensates stress induced effect of non-flatness of the substrate by the first film.

Abstract: An electrochemical plating (ECP) system is provided. The ECP system includes an ECP cell comprising a plating solution for an ECP process, a sensor configured to in situ measure an interface resistance between a plated metal and an electrolyte in the plating solution as the ECP process continues, a plating solution supply system in fluid communication with the ECP cell and configured to supply the plating solution to the ECP cell, and a control system operably coupled to the ECP cell, the sensor and the plating solution supply system. The control system is configured to compare the interface resistance with a threshold resistance and to adjust a composition of the plating solution in response to the interface resistance being below the threshold resistance.

Abstract: A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes an interconnect structure formed over a substrate and a passivation layer formed over the interconnect structure. The semiconductor device structure also includes an anti-acid layer formed in the passivation layer and a bonding layer formed on the anti-acid layer and the passivation layer. The anti-acid layer has a thickness that is greater than about 140 nm.

Abstract: A method for performing an electrochemical plating (ECP) process includes contacting a surface of a substrate with a plating solution comprising ions of a metal to be deposited, electroplating the metal on the surface of the substrate, in situ monitoring a plating current flowing through the plating solution between an anode and the substrate immersed in the plating solution as the ECP process continues, and adjusting a composition of the plating solution in response to the plating current being below a critical plating current such that voids formed in a subset of conductive lines having a highest line-end density among a plurality of conductive lines for a metallization layer over the substrate are prevented.