Patents by Inventor YAO-HUA CHEN

YAO-HUA CHEN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11657273
    Abstract: An adaptive learning power modeling method includes: sampling at least one of a plurality of network components to form a power consumption evaluation network according to at least one parameter within a parameter range; evaluating a predictive power consumption of a to-be-measured circuit by the power consumption evaluation network; training and evaluating an actual power consumption and the predictive power consumption of the to-be-measured circuit by the power consumption evaluation network to obtain an evaluation result; and performing training according to the evaluation result to determine whether to change the power consumption evaluation network.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: May 23, 2023
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yao-Hua Chen, Jing-Jia Liou, Chih-Tsun Huang, Juin-Ming Lu
  • Patent number: 11551066
    Abstract: A DNN hardware accelerator and an operation method of the DNN hardware accelerator are provided. The DNN hardware accelerator includes: a network distributor for receiving an input data and distributing respective bandwidth of a plurality of data types of a target data amount based on a plurality of bandwidth ratios of the target data amount; and a processing element array coupled to the network distributor, for communicating data of the data types of the target data amount between the network distributor based on the distributed bandwidth of the data types.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: January 10, 2023
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yao-Hua Chen, Chun-Chen Chen, Chih-Tsun Huang, Jing-Jia Liou, Chun-Hung Lai, Juin-Ming Lu
  • Publication number: 20220207323
    Abstract: A processing element architecture adapted to a convolution comprises a plurality of processing elements and a delayed queue circuit. The plurality of processing elements includes a first processing element and a second processing element, wherein the first processing element and the second processing element perform the convolution according to a shared datum at least. The delayed queue circuit connects to the first processing element and connects to the second processing element. The delayed queue circuit receives the shared datum sent by the first processing element, and sends the shared datum to the second processing element after receiving the shared datum and waiting for a time interval.
    Type: Application
    Filed: December 29, 2020
    Publication date: June 30, 2022
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yao-Hua CHEN, Yu-Xiang YEN, Wan-Shan HSIEH, Chih-Tsun HUANG, Juin-Ming LU, Jing-Jia LIOU
  • Publication number: 20210201118
    Abstract: A deep neural network (DNN) hardware accelerator including a processing element array is disclosed. The processing element array includes a processing element array, the processing element array including a plurality of processing element groups and each of the processing element groups including a plurality of processing elements. A first network connection implementation between a first processing element group of the processing element groups and a second processing element group of the processing element groups is different from a second network connection implementation between the processing elements in the first processing element group.
    Type: Application
    Filed: December 26, 2019
    Publication date: July 1, 2021
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yao-Hua CHEN, Wan-Shan HSIEH, Juin-Ming LU
  • Publication number: 20210201127
    Abstract: An adaptive learning power modeling method includes: sampling at least one of a plurality of network components to form a power consumption evaluation network according to at least one parameter within a parameter range; evaluating a predictive power consumption of a to-be-measured circuit by the power consumption evaluation network; training and evaluating an actual power consumption and the predictive power consumption of the to-be-measured circuit by the power consumption evaluation network to obtain an evaluation result; and performing training according to the evaluation result to determine whether to change the power consumption evaluation network.
    Type: Application
    Filed: December 27, 2019
    Publication date: July 1, 2021
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yao-Hua CHEN, Jing-Jia LIOU, Chih-Tsun HUANG, Juin-Ming LU
  • Patent number: 10896276
    Abstract: Disclosed are a timing estimation method and a simulator. The method is applied to a function verification model. In the method, the model issues a first access issue at a first time point; receives a first response to the first access issue from the bus at a second time point; calculates a delay time between the first and second time points; determines whether the delay time is longer than or substantially equal to a transmission time corresponding to the first access issue; issues a second access issue if yes; and issues the second access issue in a compensation time counting from the second time point if not. The compensation time is not longer than the difference between the transmission time and the delay time.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: January 19, 2021
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Mei-Ling Chi, Yao-Hua Chen, Hsun-Lun Huang, Juin-Ming Lu
  • Publication number: 20200193275
    Abstract: A DNN hardware accelerator and an operation method of the DNN hardware accelerator are provided. The DNN hardware accelerator includes: a network distributor for receiving an input data and distributing respective bandwidth of a plurality of data types of a target data amount based on a plurality of bandwidth ratios of the target data amount; and a processing element array coupled to the network distributor, for communicating data of the data types of the target data amount between the network distributor based on the distributed bandwidth of the data types.
    Type: Application
    Filed: January 15, 2019
    Publication date: June 18, 2020
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yao-Hua CHEN, Chun-Chen CHEN, Chih-Tsun HUANG, Jing-Jia LIOU, Chun-Hung LAI, Juin-Ming LU
  • Patent number: 10628627
    Abstract: An embodiment of a thermal estimation device including a temperature model generator, a temperature gradient calculator, and a thermal sensing analyzer is disclosed. The temperature model generator generates a temperature model based on an initial power consumption, an initial area and an initial coordination of a circuit module. The temperature gradient calculator substitutes at least one of a testing area, a testing power or a testing coordinate of the circuit module into the temperature model for correspondingly estimating an temperature estimation function. The thermal sensing analyzer differentiates the temperature estimation function. When an absolute value of a differential result of the temperature estimation function resulted from a constant is closest to zero or is zero, outputting the constant as an optimized parameter.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: April 21, 2020
    Assignee: Industrial Technology Research Institute
    Inventors: Yeong-Jar Chang, Ya-Ting Shyu, Juin-Ming Lu, Yao-Hua Chen, Yen-Fu Chang, Jai-Ming Lin
  • Patent number: 10412331
    Abstract: A power consumption estimation method is applied to an image with N rows of pixels, and comprises a pixel estimation procedure comprising performing an estimation sub-procedure pixel by pixel for each of a plurality of pixels in one row of the N rows of pixels to obtain a plurality of pixel energy consumption values respectively corresponding to the plurality of pixels in said one row of the N rows, and obtaining a row power consumption value corresponding to said one row of the N rows according to the plurality of pixel energy consumption values. The estimation sub-procedure comprises obtaining pixel content information corresponding to one of the plurality of pixels, and determining the pixel energy consumption value according to the pixel content information. The pixel energy consumption value indicates pixel energy consumption generated by performing a predetermined image processing procedure for said one of the plurality of pixels.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: September 10, 2019
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chun Wei Chen, Ming-Der Shieh, Juin-Ming Lu, Hsun-Lun Huang, Yao-Hua Chen
  • Patent number: 10365829
    Abstract: A memory transaction-level modeling method and a memory transaction-level modeling system are provided. The memory transaction-level modeling method is used for simulating the operation of outputting at least one command to the memory. The memory includes a plurality of banks each of which corresponds with a bank status table. The memory transaction-level modeling method includes the following steps: An event is received. Whether one of the bank status tables is needed to be updated is determined. If one of the bank status tables is needed to be updated, this bank status table is recovered according to a TMP queue. A command is outputted to the memory according to a command queue. The outputted command is stored in the TMP queue. Some of the bank status tables are updated and others of the bank status tables are kept unchanged.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: July 30, 2019
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yao-Hua Chen, Che-Wei Hsu, Juin-Ming Lu, Wei-Shiang Lin, Jing-Jia Liou, Chih-Tsun Huang
  • Publication number: 20190147135
    Abstract: An embodiment of a thermal estimation device including a temperature model generator, a temperature gradient calculator, and a thermal sensing analyzer is disclosed. The temperature model generator generates a temperature model based on an initial power consumption, an initial area and an initial coordination of a circuit module. The temperature gradient calculator substitutes at least one of a testing area, a testing power or a testing coordinate of the circuit module into the temperature model for correspondingly estimating an temperature estimation function. The thermal sensing analyzer differentiates the temperature estimation function. When an absolute value of a differential result of the temperature estimation function resulted from a constant is closest to zero or is zero, outputting the constant as an optimized parameter.
    Type: Application
    Filed: December 28, 2017
    Publication date: May 16, 2019
    Inventors: Yeong-Jar CHANG, Ya-Ting Shyu, Juin-Ming Lu, Yao-Hua Chen, Yen-Fu Chang, Jai-Ming Lin
  • Publication number: 20190068904
    Abstract: A power consumption estimation method is applied to an image with N rows of pixels, and comprises a pixel estimation procedure comprising performing an estimation sub-procedure pixel by pixel for each of a plurality of pixels in one row of the N rows of pixels to obtain a plurality of pixel energy consumption values respectively corresponding to the plurality of pixels in said one row of the N rows, and obtaining a row power consumption value corresponding to said one row of the N rows according to the plurality of pixel energy consumption values. The estimation sub-procedure comprises obtaining pixel content information corresponding to one of the plurality of pixels, and determining the pixel energy consumption value according to the pixel content information. The pixel energy consumption value indicates pixel energy consumption generated by performing a predetermined image processing procedure for said one of the plurality of pixels.
    Type: Application
    Filed: December 22, 2017
    Publication date: February 28, 2019
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chun Wei CHEN, Ming-Der SHIEH, Juin-Ming LU, Hsun-Lun HUANG, Yao-Hua CHEN
  • Publication number: 20180357337
    Abstract: Disclosed are a timing estimation method and a simulator. The method is applied to a function verification model. In the method, the model issues a first access issue at a first time point; receives a first response to the first access issue from the bus at a second time point; calculates a delay time between the first and second time points; determines whether the delay time is longer than or substantially equal to a transmission time corresponding to the first access issue; issues a second access issue if yes; and issues the second access issue in a compensation time counting from the second time point if not. The compensation time is not longer than the difference between the transmission time and the delay time.
    Type: Application
    Filed: December 15, 2017
    Publication date: December 13, 2018
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Mei-Ling Chi, Yao-Hua Chen, Hsun-Lun Huang, Juin-Ming Lu
  • Publication number: 20180074702
    Abstract: A memory transaction-level modeling method and a memory transaction-level modeling system are provided. The memory transaction-level modeling method is used for simulating the operation of outputting at least one command to the memory. The memory includes a plurality of banks each of which corresponds with a bank status table. The memory transaction-level modeling method includes the following steps: An event is received. Whether one of the bank status tables is needed to be updated is determined. If one of the bank status tables is needed to be updated, this bank status table is recovered according to a TMP queue. A command is outputted to the memory according to a command queue. The outputted command is stored in the TMP queue. Some of the bank status tables are updated and others of the bank status tables are kept unchanged.
    Type: Application
    Filed: December 27, 2016
    Publication date: March 15, 2018
    Inventors: Yao-Hua Chen, Che-Wei Hsu, Juin-Ming Lu, Wei-Shiang Lin, Jing-Jia Liou, Chih-Tsun Huang
  • Publication number: 20170169150
    Abstract: A method for system simulation includes the steps of: simulating the operation of a first circuit during N clock periods based on a first model and a simulation granularity, and adjusting the simulation granularity based on the input signal or the output signal corresponding to the first model. A non-transitory computer-readable recording medium corresponding to the method is also provided.
    Type: Application
    Filed: December 29, 2015
    Publication date: June 15, 2017
    Inventors: YAO-HUA CHEN, CHE-WEI HSU, JUIN-MING LU, TING-SHUO HSU, JING-JIA LIOU, CHIH-TSUN HUANG