Abstract: A device comprises a first transistor, a second transistor, a first contact, and a second contact. The first transistor comprises a first gate structure, first source/drain regions on opposite sides of the first gate structure, and first gate spacers spacing the first gate structure apart from the first source/drain regions. The second transistor comprises a second gate structure, second source/drain regions on opposite sides of the second gate structure, and second gate spacers spacing the second gate structure apart from the second source/drain regions. The first contact forms a first contact interface with one of the first source/drain regions. The second contact forms a second contact interface with one of the second source/drain regions. An area ratio of the first contact interface to top surface the first source/drain region is greater than an area ratio of the second contact interface to top surface of the second source/drain region.

Abstract: A device comprises a first transistor, a second transistor, a first contact, and a second contact. The first transistor comprises a first gate structure, first source/drain regions on opposite sides of the first gate structure, and first gate spacers spacing the first gate structure apart from the first source/drain regions. The second transistor comprises a second gate structure, second source/drain regions on opposite sides of the second gate structure, and second gate spacers spacing the second gate structure apart from the second source/drain regions. The first contact forms a first contact interface with one of the first source/drain regions. The second contact forms a second contact interface with one of the second source/drain regions. An area ratio of the first contact interface to top surface the first source/drain region is greater than an area ratio of the second contact interface to top surface of the second source/drain region.

Abstract: A device comprises a first transistor disposed within a first device region of a substrate and a second transistor disposed within a second device region of the substrate. The first transistor comprises first source/drain regions, a first gate structure laterally between the first source/drain regions, and first gate spacers respectively on opposite sidewalls of the first gate structure. The second transistor comprises second source/drain regions, a second gate structure laterally between the second source/drain regions, and second gate spacers respectively on opposite sidewalls of the second gate structure. The second source/drain regions of the second transistor have a maximal width greater than a maximal width of the first source/drain regions of the first transistor, but the second gate spacers of the second transistor have a thickness less than a thickness of the first gate spacers.

Abstract: A device comprises a first transistor disposed within a first device region of a substrate and a second transistor disposed within a second device region of the substrate. The first transistor comprises first source/drain regions, a first gate structure laterally between the first source/drain regions, and first gate spacers respectively on opposite sidewalls of the first gate structure. The second transistor comprises second source/drain regions, a second gate structure laterally between the second source/drain regions, and second gate spacers respectively on opposite sidewalls of the second gate structure. The second source/drain regions of the second transistor have a maximal width greater than a maximal width of the first source/drain regions of the first transistor, but the second gate spacers of the second transistor have a thickness less than a thickness of the first gate spacers.

Abstract: A method includes forming a first gate, a second gate, a third gate, and a fourth gate over a substrate, in which a first distance between the first gate and the second gate is less than a second distance between the third gate and the fourth gate. A first spacer over a sidewall of the first gate, a second spacer over a sidewall of the second gate, a third spacer over a sidewall of the third gate, and a fourth spacer over a sidewall of the fourth gate are formed. A mask layer over the first and second spacers is formed, in which the third and fourth spacers are exposed from the mask layer. The exposed third and fourth spacers are trimmed.

Abstract: A method includes forming a first gate, a second gate, a third gate, and a fourth gate over a substrate, in which a first distance between the first gate and the second gate is less than a second distance between the third gate and the fourth gate. A first spacer over a sidewall of the first gate, a second spacer over a sidewall of the second gate, a third spacer over a sidewall of the third gate, and a fourth spacer over a sidewall of the fourth gate are formed. A mask layer over the first and second spacers is formed, in which the third and fourth spacers are exposed from the mask layer. The exposed third and fourth spacers are trimmed.

Abstract: A semiconductor device includes a substrate; a first device disposed on the substrate, and the first device includes at least two first gate stacks, in which the two adjacent first gate stacks have a first distance therebetween; a plurality of first gate spacers having a first thickness disposed on opposite sidewalls of the first gate stacks; the semiconductor device further includes a second device disposed on the substrate, and the second device includes at least two second gate stacks, in which the two adjacent second gate stacks have a second distance therebetween, and the first distance is smaller than the second distance; a plurality of second gate spacers having a second thickness disposed on opposite sidewalls of the second gate stacks, and the first thickness is greater than the second thickness.

Abstract: A semiconductor device includes a substrate; a first device disposed on the substrate, and the first device includes at least two first gate stacks, in which the two adjacent first gate stacks have a first distance therebetween; a plurality of first gate spacers having a first thickness disposed on opposite sidewalls of the first gate stacks; the semiconductor device further includes a second device disposed on the substrate, and the second device includes at least two second gate stacks, in which the two adjacent second gate stacks have a second distance therebetween, and the first distance is smaller than the second distance; a plurality of second gate spacers having a second thickness disposed on opposite sidewalls of the second gate stacks, and the first thickness is greater than the second thickness.

Abstract: The present invention relates to a nano-sized photocatalytic sol and application thereof. The invention utilizes spherical nano-photocatalyst and non-spherical photocatalytic sol for coating a photocatalyst layer on a substrate. Because of the stereo, interlaced and composite structure between spherical photocatalyst and non-spherical photocatalyst, a hard and well adhesion coated layer of photocatalyst with good photocatalytic activity can be obtained without using binder.

Abstract: A method for manufacturing high performance photocatalytic filters is disclosed, which comprises the steps of: preparation of a photocatalytic material selected from a titanium dioxide (TiO2), a zinc oxide (ZnO), a tin dioxide (SnO2) and the mixtures thereof; metal-modification of the photocatalytic material with using the photo-deposition method, such as silver (Ag), gold (Au) or platinum (Pt), so as to enable the photocatalytic material to have a good photocatalytic activity and thus enable the as-prepared photocatalytic filter to photocatalytically degrade various volatile organic compounds (VOCs) and non-organic gases as well as all kinds of pollutants. The photocatalytic filter made of the aforesaid photocatalytic material enjoys a comparatively longer lifespan with persisting catalytic activity, and can be easily regenerated by a water-washing process.

Abstract: A photocatalyst composite and fabrication method thereof. The photocatalyst composite of invention comprises a photocatalyst and iron catalyst, wherein the photocatalyst is carried on the surface of the iron catalyst and the ratio of the photocatalyst to the iron catalyst is about 3:100 to 15:100. The photocatalyst composite can be used for water treatment, air treatment and soil remediation.

Abstract: The present invention relates to a nano-sized photocatalytic sol and application thereof. The invention utilizes spherical nano-photocatalyst and non-spherical photocatalytic sol for coating a photocatalyst layer on a substrate. Because of the stereo, interlaced and composite structure between spherical photocatalyst and non-spherical photocatalyst, a hard and well adhesion coated layer of photocatalyst with good photocatalytic activity can be obtained without using binder.

Abstract: The present invention relates to a photocatalytic composite material, a method for producing the same and application thereof. This invention can maintain the activity of a photocatalytic adsorbent and reduce energy consumption by immersing an adsorbent material into a nano-photocatalyst sol to immobilize the nano-sized photocatalyst on the surface of the adsorbent material without a high-temperature calcinations step or using an adhesive agent. Besides, immobilizing the photocatalytic composite material onto a filter can be applied to the equipment for cleaning environment.

Abstract: A rotary dryer. The dryer includes a rotary drum and a dehumidifier. the rotary cylinder receives dry air and wet material, wherein The wet material is rotated by the rotary drum to completely contact the dry air so that The wet material changes to grains. the dehumidifier receives wet air from the rotary drum, dehumidifies the wet air, and introduces dry air to the rotary cylinder.