Patents by Inventor Yao-Min Liu
Yao-Min Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20230299002Abstract: Various back end of line (BEOL) layer formation techniques described herein enable reduced contact resistance, reduced surface roughness, and/or increased semiconductor device performance for BEOL layers such as interconnects and/or metallization layers.Type: ApplicationFiled: March 18, 2022Publication date: September 21, 2023Inventors: Shu-Cheng CHIN, Chih-Chien CHI, Hsin-Ying PENG, Jau-Jiun HUANG, Ya-Lien LEE, Kuan-Chia CHEN, Chia-Pang KUO, Yao-Min LIU
-
Publication number: 20230275019Abstract: A semiconductor device includes an insulating layer, wherein the insulating layer has a via opening and a conductive line opening. The semiconductor device further includes a via in the via opening. The semiconductor device further includes a conductive line in the conductive line opening. The conductive line includes a first liner layer, wherein a first thickness of the first liner layer over the via is less than a second thickness of the first liner layer over the insulating layer, and a conductive fill, wherein the first liner layer surrounds the conductive fill.Type: ApplicationFiled: May 4, 2023Publication date: August 31, 2023Inventors: Shu-Cheng CHIN, Yao-Min LIU, Hung-Wen SU, Chih-Chien CHI, Chi-Feng LIN
-
Patent number: 11676898Abstract: A method includes forming an insulating layer over a conductive feature; etching the insulating layer to expose a first surface of the conductive feature; covering the first surface of the conductive feature with a sacrificial material, wherein the sidewalls of the insulating layer are free of the sacrificial material; covering the sidewalls of the insulating layer with a barrier material, wherein the first surface of the conductive feature is free of the barrier material, wherein the barrier material includes tantalum nitride (TaN) doped with a transition metal; removing the sacrificial material; and covering the barrier material and the first surface of the conductive feature with a conductive material.Type: GrantFiled: June 11, 2020Date of Patent: June 13, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Pang Kuo, Huan-Yu Shih, Wen-Hsuan Chen, Cheng-Lun Tsai, Ya-Lien Lee, Cheng-Hui Weng, Chun-Chieh Lin, Hung-Wen Su, Yao-Min Liu
-
Patent number: 11652044Abstract: A semiconductor device includes an insulating layer, wherein the insulating layer has a via opening and a conductive line opening. The semiconductor device further includes a via in the via opening, wherein the via includes a first conductive material. The semiconductor device further includes a conductive line in the conductive line opening. The conductive line includes a first liner layer, wherein a first thickness of the first liner layer over the via is less than a second thickness of the first liner layer over the insulating layer, and a conductive fill comprising a second conductive material different from the first conductive material.Type: GrantFiled: February 26, 2021Date of Patent: May 16, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shu-Cheng Chin, Yao-Min Liu, Hung-Wen Su, Chih-Chien Chi, Chi-Feng Lin
-
Publication number: 20230068398Abstract: In some implementations, one or more semiconductor processing tools may form a via within a substrate of a semiconductor device. The one or more semiconductor processing tools may deposit a ruthenium-based liner within the via. The one or more semiconductor processing tools may deposit, after depositing the ruthenium-based liner, a copper plug within the via.Type: ApplicationFiled: August 30, 2021Publication date: March 2, 2023Inventors: Yao-Min LIU, Ming-Yuan GAO, Ming-Chou CHIANG, Shu-Cheng CHIN, Huei-Wen HSIEH, Kai-Shiang KUO, Yen-Chun LIN, Cheng-Hui WENG, Chun-Chieh LIN, Hung-Wen SU
-
Publication number: 20230042277Abstract: A semiconductor processing tool performs passivation layer deposition and removal in situ. A transport mechanism included in the semiconductor processing tool transfers a semiconductor structure through different deposition chambers (e.g., without breaking or removing a vacuum environment). Accordingly, the semiconductor processing tool deposits a target layer that is thinner on, or even absent from, a metal layer, such that contact resistance is reduced between a conductive structure formed over the target layer and the metal layer. As a result, electrical performance of a device including the conductive structure is improved. Moreover, because the process is performed in situ (e.g., without breaking or removing the vacuum) in the semiconductor processing tool, production time and risk of impurities in the conductive structure are reduced. As a result, throughput is increased, and chances of spoiled wafers are decreased.Type: ApplicationFiled: March 7, 2022Publication date: February 9, 2023Inventors: Chia-Pang KUO, Yao-Min LIU, Shu-Cheng CHIN, Chih-Chien CHI, Cheng-Hui WENG
-
Patent number: 11527476Abstract: A semiconductor structure and a method of forming the same are provided. A method includes depositing a dielectric layer over a conductive feature. The dielectric layer is patterned to form an opening therein. The opening exposes a first portion of the conductive feature. A first barrier layer is deposited on a sidewall of the opening. The first portion of the conductive feature remains exposed at the end of depositing the first barrier layer.Type: GrantFiled: January 7, 2021Date of Patent: December 13, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yao-Min Liu, Chia-Pang Kuo, Chien Chung Huang, Chih-Yi Chang, Ya-Lien Lee, Chun-Chieh Lin, Hung-Wen Su, Ming-Hsing Tsai
-
Publication number: 20220384338Abstract: A method of making a semiconductor device includes etching an insulating layer to form a first opening and a second opening. The method further includes depositing a conductive material in the first opening. The method further includes performing a surface modification process on the conductive material. The method further includes depositing, after the surface modification process, a first liner layer in the second opening, wherein the first liner layer extends over the conductive material and the insulating layer. The method further includes depositing a conductive fill over the first liner layer, wherein the conductive fill includes a different material from the conductive material.Type: ApplicationFiled: August 10, 2022Publication date: December 1, 2022Inventors: Shu-Cheng CHIN, Yao-Min LIU, Hung-Wen SU, Chih-Chien CHI, Chi-Feng LIN
-
Publication number: 20220367376Abstract: A method includes forming an insulating layer over a conductive feature; etching the insulating layer to expose a first surface of the conductive feature; covering the first surface of the conductive feature with a sacrificial material, wherein the sidewalls of the insulating layer are free of the sacrificial material; covering the sidewalls of the insulating layer with a barrier material, wherein the first surface of the conductive feature is free of the barrier material, wherein the barrier material includes tantalum nitride (TaN) doped with a transition metal; removing the sacrificial material; and covering the barrier material and the first surface of the conductive feature with a conductive material.Type: ApplicationFiled: July 26, 2022Publication date: November 17, 2022Inventors: Chia-Pang Kuo, Huan-Yu Shih, Wen-Hsuan Chen, Cheng-Lun Tsai, Ya-Lien Lee, Cheng-Hui Weng, Chun-Chieh Lin, Hung-Wen Su, Yao-Min Liu
-
Publication number: 20220278040Abstract: A semiconductor device includes an insulating layer, wherein the insulating layer has a via opening and a conductive line opening. The semiconductor device further includes a via in the via opening, wherein the via includes a first conductive material. The semiconductor device further includes a conductive line in the conductive line opening. The conductive line includes a first liner layer, wherein a first thickness of the first liner layer over the via is less than a second thickness of the first liner layer over the insulating layer, and a conductive fill comprising a second conductive material different from the first conductive material.Type: ApplicationFiled: February 26, 2021Publication date: September 1, 2022Inventors: Shu-Cheng CHIN, Yao-Min LIU, Hung-Wen SU, Chih-Chien CHI, Chi-Feng LIN
-
Publication number: 20220165616Abstract: A method includes forming a first conductive feature in a first dielectric layer. A second dielectric layer is formed over the first conductive feature and the first dielectric layer. An opening is formed in the second dielectric layer. The opening exposes a top surface of the first conductive feature. The top surface of the first conductive feature includes a first metallic material and a second metallic material different from the first metallic material. A native oxide layer is removed from the top surface of the first conductive feature. A surfactant soaking process is performed on the top surface of the first conductive feature. The surfactant soaking process forms a surfactant layer over the top surface of the first conductive feature. A first barrier layer is deposited on a sidewall of the opening. The surfactant layer remains exposed at the end of depositing the first barrier layer.Type: ApplicationFiled: February 11, 2022Publication date: May 26, 2022Inventors: Yao-Min Liu, Chia-Pang Kuo, Shu-Cheng Chin, Chih-Chien Chi, Cheng-Hui Weng, Hung-Wen Su, Ming-Hsing Tsai
-
Publication number: 20220084937Abstract: A semiconductor structure and a method of forming the same are provided. A method includes depositing a dielectric layer over a conductive feature. The dielectric layer is patterned to form an opening therein. The opening exposes a first portion of the conductive feature. A first barrier layer is deposited on a sidewall of the opening. The first portion of the conductive feature remains exposed at the end of depositing the first barrier layer.Type: ApplicationFiled: January 7, 2021Publication date: March 17, 2022Inventors: Yao-Min Liu, Chia-Pang Kuo, Chien Chung Huang, Chih-Yi Chang, Ya-Lien Lee, Chun-Chieh Lin, Hung-Wen Su, Ming-Hsing Tsai
-
Publication number: 20210391275Abstract: A method includes forming an insulating layer over a conductive feature; etching the insulating layer to expose a first surface of the conductive feature; covering the first surface of the conductive feature with a sacrificial material, wherein the sidewalls of the insulating layer are free of the sacrificial material; covering the sidewalls of the insulating layer with a barrier material, wherein the first surface of the conductive feature is free of the barrier material, wherein the barrier material includes tantalum nitride (TaN) doped with a transition metal; removing the sacrificial material; and covering the barrier material and the first surface of the conductive feature with a conductive material.Type: ApplicationFiled: June 11, 2020Publication date: December 16, 2021Inventors: Chia-Pang Kuo, Huan-Yu Shih, Wen-Hsuan Chen, Cheng-Lun Tsai, Ya-Lien Lee, Cheng-Hui Weng, Chun-Chieh Lin, Hung-Wen Su, Yao-Min Liu
-
Patent number: 9156947Abstract: An organic semiconductor material is provided. The organic semiconductor material includes a compound represented by formula (1): wherein r and s each independently represent a positive integer of 1 to 20; n represents a positive integer of 2 to 10000; X1, X2 and X3 each independently represent O, S, Se, Te, NR, RCR, RSiR, RGeR or RSnR; Y1 and Y2 each independently represent H, F, Cl, CF3, haloalkyl, CN, R, OR, SR, COOR or COR; and Z1, Z2, Z3 and Z4 each independently represent H, F, Cl, CF3, haloalkyl, CN, R, OR, SR, COOR or COR, wherein R represents alkyl group.Type: GrantFiled: August 29, 2013Date of Patent: October 13, 2015Assignee: Au Optronics CorporationInventors: Chain-Shu Hsu, Jhong-Sian Wu, Jyun-Fong Jheng, Chien-Lung Wang, Ching-Yang Liu, Yao-Min Liu
-
Publication number: 20140312317Abstract: An organic semiconductor material is provided. The organic semiconductor material includes a compound represented by formula (1): wherein r and s each independently represent a positive integer of 1 to 20; n represents a positive integer of 2 to 10000; X1, X2 and X3 each independently represent O, S, Se, Te, NR, RCR, RSiR, RGeR or RSnR; Y1 and Y2 each independently represent H, F, Cl, CF3, haloalkyl, CN, R, OR, SR, COOR or COR; and Z1, Z2, Z3 and Z4 each independently represent H, F, Cl, CF3, haloalkyl, CN, R, OR, SR, COOR or COR, wherein R represents alkyl group.Type: ApplicationFiled: August 29, 2013Publication date: October 23, 2014Applicant: Au Optronics CorporationInventors: Chain-Shu Hsu, Jhong-Sian Wu, Jyun-Fong Jheng, Chien-Lung Wang, Ching-Yang Liu, Yao-Min Liu