Patents by Inventor Yao-Pin Wang

Yao-Pin Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12001571
    Abstract: A method of operating a user device includes: receiving a command from a user to power on the user device, wherein the user device includes information on a restricted zone associated with the user device; detecting, by a monitoring entity of the user device without involvement of any device external to the user device, whether the user device is located within the restricted zone in response to the user device being powered on and before an operating system of the user device is executed; and granting access of the user to the user device by the monitoring entity in response to detecting the user device as being within the restricted zone.
    Type: Grant
    Filed: November 3, 2022
    Date of Patent: June 4, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Wen-Chang Kuo, Chiang Kao, Kuo Hsiung Chen, Ho-Han Liu, Ti-Yen Yang, Jo-Chan Liu, Chi-Pin Wang, Yao-Hsiung Chang
  • Patent number: 11431440
    Abstract: An iterative detection and decoding (IDD) circuit is provided. The iterative detection and decoding (IDD) circuit is configured to perform M outer iterations on a received signal, and Ni inner iterations are performed during the ith outer iteration of the M outer iterations, where M is an integer greater than 1, i is an integer less than or equal to M, and N1 to NM are integers and include at least two different values.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: August 30, 2022
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Chia-Hsiang Yang, Yao-Pin Wang, Chi-Chih Wen, Der-Zheng Liu, Chung-Jung Huang
  • Publication number: 20200295864
    Abstract: An iterative detection and decoding (IDD) circuit is provided. The iterative detection and decoding (IDD) circuit is configured to perform M outer iterations on a received signal, and Ni inner iterations are performed during the ith outer iteration of the M outer iterations, where M is an integer greater than 1, i is an integer less than or equal to M, and N1 to NM are integers and include at least two different values.
    Type: Application
    Filed: June 28, 2019
    Publication date: September 17, 2020
    Inventors: Chia-Hsiang YANG, Yao-Pin Wang, Chi-Chih Wen, Der-Zheng Liu, Chung-Jung Huang