Abstract: This document describes apparatuses and techniques for providing a flexible connector between a secondary circuit board and a main logic board with a permeability shield to increase impedance of the flexible connector to reduce antenna loss from an antenna via the flexible connector to the main logic board. For example, an apparatus includes a secondary circuit board supporting one or more control pads and an antenna. A flexible connector includes a plurality of conductive traces configured to electrically couple the one or more control pads of the secondary circuit board to a coupling on a main logic board. A permeability shield is configured to be disposed along one or more portions of the flexible connector. The permeability shield is configured to increase impedance of the flexible connector to reduce antenna loss of the antenna via the control pads and the flexible connector to the main logic board.

Abstract: A semiconductor structure and a fabrication method of the semiconductor structure are provided. The semiconductor structure includes a substrate. The substrate includes a first region, a second region, and an isolation region between the first region and the second region. The semiconductor structure also includes a first fin, a second fin and a third fin disposed over the first region, the second region, and the isolation region, respectively. Further, the semiconductor structure includes a gate structure. The gate structure includes a first work function layer over the first region and a first portion of the isolation region, and a second work function layer over the second region and a second portion of the isolation region. An interface where the first work function layer is in contact with the second work function layer is located over a top surface of the third fin.

Abstract: The present disclosure provides a semiconductor device manufacturing method. The method includes: providing a semiconductor substrate, including a high-frequency-block group and a low-power-block group; forming high-frequency-type logic standard cells on the high-frequency-block group of the semiconductor substrate. The high-frequency-type logic standard cells have a high-frequency-type cell height, a high-frequency-type operating frequency, and a high-frequency-type power. The method further includes forming low-power-type logic standard cells on the low-power-block group of the semiconductor substrate. The low-power-type logic standard cells have a low-power-type cell height, a low-power-type operating frequency, and a low-power-type power.

Abstract: A semiconductor structure and a fabrication method of the semiconductor structure are provided. The semiconductor structure includes a substrate. The substrate includes a first region, a second region, and an isolation region between the first region and the second region. The semiconductor structure also includes a first fin, a second fin and a third fin disposed over the first region, the second region, and the isolation region, respectively. Further, the semiconductor structure includes a gate structure. The gate structure includes a first work function layer over the first region and a first portion of the isolation region, and a second work function layer over the second region and a second portion of the isolation region. An interface where the first work function layer is in contact with the second work function layer is located over a top surface of the third fin.

Abstract: The present disclosure provides a semiconductor device manufacturing method. The method includes: providing a semiconductor substrate, including a high-frequency-block group and a low-power-block group; forming high-frequency-type logic standard cells on the high-frequency-block group of the semiconductor substrate. The high-frequency-type logic standard cells have a high-frequency-type cell height, a high-frequency-type operating frequency, and a high-frequency-type power. The method further includes forming low-power-type logic standard cells on the low-power-block group of the semiconductor substrate.

Abstract: The present disclosure provides a semiconductor device and a manufacturing method thereof. The semiconductor device includes: a semiconductor substrate including a high-frequency-block group and a low-power-block group; high-frequency-type logic standard cells located on the high-frequency-block group, and having a high-frequency-type cell height, a high-frequency-type operating frequency, and a high-frequency-type power; low-power-type logic standard cells located on the low-power-block group, and having a low-power-type cell height, a low-power-type operating frequency, and a low-power-type power. The high-frequency-type cell height is higher than the low-power-type cell height. The high-frequency-type operating frequency is greater than the low-power-type operating frequency. The high-frequency-type power is greater than the low-power-type power. The high-frequency-type logic standard cells include high-frequency-type fins, and the low-power-type logic standard cells include low-power-type fins.

Abstract: The present disclosure provides a semiconductor device and a manufacturing method thereof. The semiconductor device includes: a semiconductor substrate including a high-frequency-block group and a low-power-block group; high-frequency-type logic standard cells located on the high-frequency-block group, and having a high-frequency-type cell height, a high-frequency-type operating frequency, and a high-frequency-type power; low-power-type logic standard cells located on the low-power-block group, and having a low-power-type cell height, a low-power-type operating frequency, and a low-power-type power. The high-frequency-type cell height is higher than the low-power-type cell height. The high-frequency-type operating frequency is greater than the low-power-type operating frequency. The high-frequency-type power is greater than the low-power-type power. The high-frequency-type logic standard cells include high-frequency-type fins, and the low-power-type logic standard cells include low-power-type fins.

Abstract: A method and a system for providing customizable, process-specific Just-In-Time debugging in operating system is provide in this invention. The method comprises the following steps: obtaining process-specific JIT debugging information, in response to the occurrence of an trap event in operating system; invoking the debugger corresponding to the process according to the obtained process-specific JIT debugging information. This method and system supports per-process JIT debugging configuration.

Abstract: A method and system for invoking Just-In-Time debugger is described, which can provide more efficient JIT debugging for complex code mixed applications. A method for invoking a Just-In-Time (JIT) debugger according to one embodiment includes checking a code type of a code address where a JIT debugging request is triggered from a process of a code-mixed application in response to the JIT debugging request from the process; acquiring corresponding JIT debugging information for different code types of the code-mixed application; and invoking a JIT debugger corresponding to the code type in response to the checked code type of the code address in the process and the acquired corresponding JIT debugging information.

Abstract: Dynamic help information is provided by receiving unit, configured to receive at least one operation of a user and to obtain the user's operation history, where the operation history includes at least one operation; a determining unit, configured to determine the corresponding help information according to the user's operation history; and an information obtaining unit, configured to obtain said corresponding help information. Assistance in providing help information is also provided, comprising: an operation capturing unit, configured to capture and send at least one operation of a user; and an information displaying unit, configured to receive and display the help information corresponding to the user's operation history, where the operation history includes at least one operation. With the apparatuses and method of this invention, the pertinent help information can be dynamically provided for users according to user's operation history.

Abstract: Web services are automatically generated from corresponding Web applications under service-oriented architecture. A Web service is generated based on a Web application, comprising: obtaining user input information of the Web application, obtaining call stack information that is generated by the Web application at runtime based on the user input information, performing parameter matching between the user input information and the call stack information, selecting a method from the call stack information as an application programming interface based on a result of the parameter matching and the call stack information, and generating the Web service using the application programming interface.

Abstract: The present invention relates to a technology for deadlock detection in a program, and more particularly relates to a technology for detecting deadlock in a program through lock graph analysis. The present invention provides a method for detecting deadlock, comprising: obtaining lock information related to locking operation in a program; generating a first lock graph based on the obtained lock information, wherein each node in the first lock graph comprises a set of locks comprising at least one lock and a set of program locations comprising at least one lock location; extracting a strongly connected sub graph in the first lock graph; unfolding the strongly connected sub graph in the first lock graph to generate a second lock graph, wherein each node in the second lock graph comprises a single lock; and extracting a strongly connected sub graph in the second lock graph, the strongly connected sub graph in the second lock graph indicating a deadlock in the program.

Abstract: A deadlock detection method and computer system for parallel programs. A determination is made that a lock of the parallel programs is no longer used in a running procedure of the parallel programs. A node corresponding to the lock that is no longer used, and edges relating to the lock that is no longer used, are deleted from a lock graph corresponding to the running procedure of the parallel programs in order to acquire an updated lock graph. The lock graph is constructed according to a lock operation of the parallel programs. Deadlock detection is then performed on the updated lock graph.

Abstract: A method and system for facilitating runtime memory analysis. The method includes: assigning a unique ID for each task in a running program; recording memory access events occurring during the running program, including the IDs of the task performing the memory accesses; issuing a task termination notification in response to a task terminating, the task termination notification including the ID of the terminating task; and releasing all the memory access events having the ID of the terminating task in the memory, in response to the task termination notification. This method and system can ensure that the memory access events stored in the memory will not increase unlimitedly, so that the memory overhead is reduced remarkably and dynamic memory analysis can be faster and more efficient.

Abstract: The present invention relates to a technology for deadlock detection in a program, and more particularly relates to a technology for detecting deadlock in a program through lock graph analysis. The present invention provides a method for detecting deadlock, comprising: obtaining lock information related to locking operation in a program; generating a first lock graph based on the obtained lock information, wherein each node in the first lock graph comprises a set of locks comprising at least one lock and a set of program locations comprising at least one lock location; extracting a strongly connected sub graph in the first lock graph; unfolding the strongly connected sub graph in the first lock graph to generate a second lock graph, wherein each node in the second lock graph comprises a single lock; and extracting a strongly connected sub graph in the second lock graph, the strongly connected sub graph in the second lock graph indicating a deadlock in the program.

Abstract: A method and/or system for detecting deadlock, comprising: obtaining lock information related to locking operation in a program; generating a first lock graph based on the obtained lock information, wherein each node in the first lock graph comprises a set of locks comprising at least one lock and a set of program locations comprising at least one lock location; extracting a strongly connected sub graph in the first lock graph; unfolding the strongly connected sub graph in the first lock graph to generate a second lock graph, wherein each node in the second lock graph comprises a single lock; and extracting a strongly connected sub graph in the second lock graph, the strongly connected sub graph in the second lock graph indicating a deadlock in the program.

Abstract: A method and system of deadlock detection in a parallel program, the method comprising: recording lock events during the operation of the parallel program and a first order relation among the lock events; converting information relevant to the operation of the parallel program into gate lock events and recording the gate lock events; establishing a second order relation among the gate lock events and lock events associated with the gate lock events and adding the second order relation to the first order relation; constructing a lock graph corresponding to the operation procedure of the parallel program based on the added first order relation; and performing deadlock detection on the constructed lock graph. The deadlock detection method of the invention can improve the accuracy of deadlock detection without depending on the deadlock detection algorithm per se, and can be applied with facility to various development environments and reduce development costs.

Abstract: The present invention provides a method and system for processing memory access events.

Abstract: A method of accessing a shared data structure in parallel by multiple threads in a parallel application program is disclosed. A lock of the shared data structure is granted to one thread of the multiple threads, an operation of the thread which acquires the lock is performed on the shared data structure, an operation of each thread of the multiple threads which does not acquire the lock is buffered, and the buffered operations are performed on the shared data structure when another thread of the multiple threads subsequently acquires the lock. A corresponding apparatus and program product are also disclosed.

Abstract: One aspect of the invention provides a method for implementing a colonial relationship in a multiplayer online game. The method includes: receiving instructions from a first entity to attack a second entity; determining whether the first entity's attack is successful; and if the first entity's attack is successful, establishing a colonial relationship between the second entity and the first entity, wherein a portion of production of the second entity is transferred to the first entity.