Abstract: Aspects of the disclosure provide a frame processor for processing frames with aliasing artifacts. For example, the frame processor can include a super-resolution (SR) and anti-aliasing (AA) engine and an attention reference frame generator coupled to the SR and AA engine. The SR and AA engine can be configured to enhance resolution and remove aliasing artifacts of a frame to generate a first high-resolution frame with aliasing artifacts and a second high-resolution frame with aliasing artifacts removed. The attention reference frame generator can be configured to generate an attention reference frame based on the first high-resolution frame and the second high-resolution frame.

Abstract: A sterilization apparatus for a portable electronic device including a cabinet and a carrier is provided. The carrier includes a base slidably disposed on the cabinet, multiple first positioning elements and multiple second positioning elements disposed in parallel on the base, multiple sterilization light sources corresponding to the second positioning elements and multiple pressure sensors disposed in parallel in the base. The base is configured to carry at least one portable electronic device. One second positioning element is disposed between any two adjacent first positioning elements, and any first positioning element and any second positioning element adjacent to each other are separated by a positioning space. The pressure sensors are respectively located in the positioning spaces. One sterilization light source is disposed between any two adjacent pressure sensors, and the pressure sensors are configured to sense a pressure from the portable electronic device.

Abstract: A semiconductor device with different configurations of gate structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a gate opening on the fin structure, forming a metallic oxide layer within the gate opening, forming a first dielectric layer on the metallic oxide layer, forming a second dielectric layer on the first dielectric layer, forming a work function metal (WFM) layer on the second dielectric layer, and forming a gate metal fill layer on the WFM layer. The forming the first dielectric layer includes depositing an oxide material with an oxygen areal density less than an oxygen areal density of the metallic oxide layer.

Abstract: An aluminum plastic film for a lithium battery and a method for manufacturing the same are provided. The method includes steps as follows: preparing a polyolefin adhesive; coating the polyolefin adhesive onto one surface of an aluminum foil layer; disposing an inner polyolefin layer onto the polyolefin adhesive; and drying the polyolefin adhesive, so that a polyolefin adhesive layer is formed between the aluminum foil layer and the inner polyolefin layer. Components of the polyolefin adhesive include a modified polyolefin polymer and a hardener. The modified polyolefin polymer has a modified group, a structure of the modified group contains maleic anhydride, and a molecular weight of the modified polyolefin polymer ranges from 100,000 g/mol to 200,000 g/mol.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first source/drain epitaxial feature formed over a substrate, a second source/drain epitaxial feature formed over the substrate, two or more semiconductor layers disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature, a gate electrode layer surrounding a portion of one of the two or more semiconductor layers, a first dielectric region disposed in the substrate and in contact with a first side of the first source/drain epitaxial feature, and a second dielectric region disposed in the substrate and in contact with a first side of the second source/drain epitaxial feature, the second dielectric region being separated from the first dielectric region by a substrate.

Abstract: Electrodeposited copper foils having adequate puncture strength to withstand both pressure application during consolidation with negative electrode active materials during manufacture, as well as expansion/contraction during repeated charge/discharging cycles when used in a rechargeable secondary battery are described. These copper foils find specific utility as current collectors in rechargeable secondary batteries, particularly in lithium secondary battery with high capacity. Methods of making the copper foils, methods of producing negative electrode for use in lithium secondary battery and lithium secondary battery of high capacity are also described.

Abstract: Provided are an electrolytic copper foil, an electrode and a lithium-ion cell comprising the same. The electrolytic copper foil has a first surface and a second surface opposite the first surface. An absolute difference of the FWHM of the characteristic peaks of (111) planes of the first surface and the second surface analyzed by GIXRD is less than 0.14, the first and the second surfaces each have a nanoindentation hardness of 0.3 GPa to 3.0 GPa, and the yield strength of the electrolytic copper foil is more than 230 MPa. By controlling the absolute difference of the FWHM of the characteristic peaks of (111) plane of these two surfaces, the nanoindentation hardness of these two surfaces and the yield strength, the electrolytic copper foil can have improved tolerance to the repeated charging and discharging and reduced warpage, thereby improving the yield rate and value of the lithium-ion cell.

Abstract: A quadrant alternate switching phase interpolator includes first and second multiplexer circuits, a phase interpolator circuitry, and a controller circuitry. The first multiplexer circuit outputs one of first and second clock signals to be a first signal in response to first and third bits in a quadrant control code. The second multiplexer circuit outputs one of third and fourth clock signals to be a second signal in response to second and fourth bits in the quadrant control code, and the first, the third, the second, and fourth clock signals are sequentially different in phase by 90 degrees. The phase interpolator circuitry generates an output clock signal in response to the first and the second signals and phase control bits. The controller circuitry performs a bit-shift operation on the phase control bits to adjust a phase of the output clock signal.

Abstract: An IC structure includes a first active area including a first plurality of fin structures extending in a first direction, a second active area including a second plurality of fin structures extending in the first direction, an electrical fuse (eFuse) extending in the first direction between the first and second active areas and electrically connected to each of the first and second pluralities of fin structures, a first plurality of gate structures extending over the first active area perpendicular to the first direction, a second plurality of gate structures extending over the second active area in the second direction, a first signal line extending in the first direction adjacent to the first active area and electrically connected to the first plurality of gate structures, and a second signal line extending in the first direction adjacent to the second active area and electrically connected to the second plurality of gate structures.

Abstract: An embodiment interfacial bonding test structure may include a first substrate having a first planar surface, a second substrate having a second planar surface that is parallel to the first planar surface, a first semiconductor die, and a second semiconductor die, each semiconductor die bonded between the first substrate and the second substrate thereby forming a sandwich structure. The first semiconductor die and the second semiconductor die may be bonded to the first surface with a first adhesive and may be bonded to the second surface with a second adhesive. The first semiconductor die and the second semiconductor die may be displaced from one another by a first separation along a direction parallel to the first planar surface and the second planar surface. The second substrate may include a notch having an area that overlaps with an area of the first separation in a plan view.

Abstract: An antifuse structure and IC devices incorporating such antifuse structures in which the antifuse structure includes an dielectric antifuse structure formed on an active area having a first dielectric antifuse electrode, a second dielectric antifuse electrode extending parallel to the first dielectric antifuse electrode, a first dielectric composition between the first dielectric antifuse electrode and the second dielectric antifuse electrode, and a first programming transistor electrically connected to a first voltage supply wherein, during a programming operation a programming voltage is selectively applied to certain of the dielectric antifuse structures to form a resistive direct electrical connection between the first dielectric antifuse electrode and the second dielectric antifuse electrode.

Abstract: A foot sensor and analysis device, which includes a pressure sensing layer arranged inside the insole and a sensing module installed inside the insole. The sensing module is electrically coupled with the pressure sensing layer for receiving and processing detected electronic signals, where sensing module includes an inductance coil to perform wireless charging to the battery. The pressure sensing layer and the sensing module are integrally formed inside the insole.

Abstract: A memory bit cell includes a first memory cell including a first antifuse transistor and a first selection transistor, the first antifuse transistor being selectable between a first state or a second state in response to a word line program signal, the first selection transistor being configured to provide access to the first antifuse transistor in response to a word line read signal; a second memory cell including a second antifuse transistor and a second selection transistor, the second antifuse transistor being selectable between the first state or the second state in response to the word line program signal, the second selection transistor being configured to provide access to the second antifuse transistor in response to the word line read signal; a first word line to selectively provide the word line program signal; a second word line to selectively provide the word line read signal; and a bit line.

Abstract: A semiconductor package includes a substrate and at least one integrated circuit (IC) die. Substrate solder resist has substrate solder resist openings exposing substrate bonding pads of the bonding surface of the substrate, and die solder resist has aligned die solder resist openings exposing die bonding pads of the bonding surface of the IC die. A ball grid array (BGA) electrically connects the die bonding pads with substrate bonding pads via the die solder resist openings and the substrate solder resist openings. The die solder resist openings include a subset A of the die solder resist openings in a region A of the bonding surface of the IC die and a subset B of the die solder resist openings in a region B of the bonding surface of the IC die. The die solder resist openings of subset A are larger than those of subset B.

Abstract: Resource optimized forwarding of classified requests to different instances of a microservice is provided. The process includes obtaining classified requests to a microservice. The classified requests are classified based on different microservice resource consumption types. Further, the method includes forwarding the classified requests to instances of the microservice with different assigned resource configurations. The forwarding is based on the different microservice resource consumption types of the classified requests.

Abstract: A semiconductor device with different configurations of gate structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a gate opening on the fin structure, forming a metallic oxide layer within the gate opening, forming a first dielectric layer on the metallic oxide layer, forming a second dielectric layer on the first dielectric layer, forming a work function metal (WFM) layer on the second dielectric layer, and forming a gate metal fill layer on the WFM layer. The forming the first dielectric layer includes depositing an oxide material with an oxygen areal density less than an oxygen areal density of the metallic oxide layer.

Abstract: The present invention discloses a neckband sensing device including a processor; a sensor is coupled to the processor, the sensor is selected form a blood pressure sensor, a heart rate sensor, an infrared sensor, a temperature sensor, an ultrasonic sensor, piezoelectric vibration sensor or the combination thereof. A light therapy device is coupled with the processor to emit therapy light.

Abstract: A semiconductor structure includes a first fin structure and a second fin structure, a first dielectric layer disposed over the first fin structure, a second dielectric layer disposed over the second fin structure, a first gate electrode disposed over the first dielectric layer, and a second gate electrode disposed over the second dielectric layer. A thickness of the first dielectric layer and a thickness of the second dielectric layer are equal. The second fin structure includes an outer region and an inner region, and a Ge concentration in the outer portion is less than Ge concentration in the inner portion.

Abstract: A semiconductor device includes a semiconductor substrate, an interfacial layer formed on the semiconductor substrate, a high-k dielectric layer formed on the interfacial layer, and a conductive gate electrode layer formed on the high-k dielectric layer. At least one of the high-k dielectric layer and the interfacial layer is doped with: a first dopant species, a second dopant species, and a third dopant species. The first dopant species and the second dopant species form a plurality of first dipole elements having a first polarity. The third dopant species forms a plurality of second dipole elements having a second polarity, and the first and second polarities are opposite.