Abstract: A semiconductor device with different configurations of gate structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a gate opening on the fin structure, forming a metallic oxide layer within the gate opening, forming a first dielectric layer on the metallic oxide layer, forming a second dielectric layer on the first dielectric layer, forming a work function metal (WFM) layer on the second dielectric layer, and forming a gate metal fill layer on the WFM layer. The forming the first dielectric layer includes depositing an oxide material with an oxygen areal density less than an oxygen areal density of the metallic oxide layer.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first source/drain epitaxial feature formed over a substrate, a second source/drain epitaxial feature formed over the substrate, two or more semiconductor layers disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature, a gate electrode layer surrounding a portion of one of the two or more semiconductor layers, a first dielectric region disposed in the substrate and in contact with a first side of the first source/drain epitaxial feature, and a second dielectric region disposed in the substrate and in contact with a first side of the second source/drain epitaxial feature, the second dielectric region being separated from the first dielectric region by a substrate.

Abstract: An IC structure includes a first active area including a first plurality of fin structures extending in a first direction, a second active area including a second plurality of fin structures extending in the first direction, an electrical fuse (eFuse) extending in the first direction between the first and second active areas and electrically connected to each of the first and second pluralities of fin structures, a first plurality of gate structures extending over the first active area perpendicular to the first direction, a second plurality of gate structures extending over the second active area in the second direction, a first signal line extending in the first direction adjacent to the first active area and electrically connected to the first plurality of gate structures, and a second signal line extending in the first direction adjacent to the second active area and electrically connected to the second plurality of gate structures.

Abstract: An antifuse structure and IC devices incorporating such antifuse structures in which the antifuse structure includes an dielectric antifuse structure formed on an active area having a first dielectric antifuse electrode, a second dielectric antifuse electrode extending parallel to the first dielectric antifuse electrode, a first dielectric composition between the first dielectric antifuse electrode and the second dielectric antifuse electrode, and a first programming transistor electrically connected to a first voltage supply wherein, during a programming operation a programming voltage is selectively applied to certain of the dielectric antifuse structures to form a resistive direct electrical connection between the first dielectric antifuse electrode and the second dielectric antifuse electrode.

Abstract: A memory bit cell includes a first memory cell including a first antifuse transistor and a first selection transistor, the first antifuse transistor being selectable between a first state or a second state in response to a word line program signal, the first selection transistor being configured to provide access to the first antifuse transistor in response to a word line read signal; a second memory cell including a second antifuse transistor and a second selection transistor, the second antifuse transistor being selectable between the first state or the second state in response to the word line program signal, the second selection transistor being configured to provide access to the second antifuse transistor in response to the word line read signal; a first word line to selectively provide the word line program signal; a second word line to selectively provide the word line read signal; and a bit line.

Abstract: An electronic device is provided, including a housing, a first slot, a second slot, and a circuit board. The first and second slots are formed on the housing and spaced apart from each other. The circuit board is disposed in the housing and includes a first antenna structure and a second antenna structure. The first antenna structure has a Z-shaped conductive body, and the second antenna structure includes a microstrip portion and a base portion. The base portion is electrically connected to the conductive body, and the microstrip portion is spaced apart from the base portion.

Abstract: An electronic device is provided, including a housing, a first slot, a second slot, and a circuit board. The first and second slots are formed on the housing and spaced apart from each other. The circuit board is disposed in the housing and includes a first antenna structure and a second antenna structure. The first antenna structure has a Z-shaped conductive body, and the second antenna structure includes a microstrip portion and a base portion. The base portion is electrically connected to the conductive body, and the microstrip portion is spaced apart from the base portion.

Abstract: A training apparatus and a training method for providing a sample size expanding model are provided. A normalizing unit receives a training data set with at least one numeric predictor factor and a numeric response factor. An encoding unit trains the training data set in an initial encoding layer and at least one deep encoding layer. A modeling unit extracts a mean vector and a variance vector and inputting the mean vector and the variance vector together into a latent hidden layer for obtaining the sample size expanding model. A decoding unit trains the training data set in at least one deep decoding layer and a last encoding layer. A verifying unit performs a verification of the sample size expanding model according to the outputting data set. A data generating unit generates a plurality of samples via the sample size expanding model.

Abstract: A training apparatus and a training method for providing a sample size expanding model are provided. A normalizing unit receives a training data set with at least one numeric predictor factor and a numeric response factor. An encoding unit trains the training data set in an initial encoding layer and at least one deep encoding layer. A modeling unit extracts a mean vector and a variance vector and inputting the mean vector and the variance vector together into a latent hidden layer for obtaining the sample size expanding model. A decoding unit trains the training data set in at least one deep decoding layer and a last encoding layer. A verifying unit performs a verification of the sample size expanding model according to the outputting data set. A data generating unit generates a plurality of samples via the sample size expanding model.

Abstract: The present invention provides a method for single-ended compensation of an operational amplifier, which comprises: designing an operational amplifier having a single-ended offset style, preparing a common-mode circuit, a switch circuit, a comparator, a digital circuit and a compensation circuits. When a single-ended offset voltage of the operational amplifier is converted, output of the comparator will change state and will be detected by the digital circuit, so that the digital circuit will fix a group of digital signals, and instruct the switch circuit to block an average signal of the common-mode circuit, allowing a set of double-end input signals to be inputted to the operational amplifier directly.

Abstract: The present invention provides a method for single-end compensation of an operational amplifier, which comprises: designing an operational amplifier having a single-end offset style, preparing a common-mode circuit, a switch circuit, a comparator, a digital circuit and a compensation circuits. When a single-end offset voltage of the operational amplifier is converted, output of the comparator will change state and will be detected by the digital circuit, so that the digital circuit will fix a group of digital signals, and instruct the switch circuit to block an average signal of the common mode circuit, allowing a set of double-end input signals to be inputted to the operational amplifier directly.