Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first source/drain epitaxial feature formed over a substrate, a second source/drain epitaxial feature formed over the substrate, two or more semiconductor layers disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature, a gate electrode layer surrounding a portion of one of the two or more semiconductor layers, a first dielectric region disposed in the substrate and in contact with a first side of the first source/drain epitaxial feature, and a second dielectric region disposed in the substrate and in contact with a first side of the second source/drain epitaxial feature, the second dielectric region being separated from the first dielectric region by a substrate.

Abstract: Electrodeposited copper foils having adequate puncture strength to withstand both pressure application during consolidation with negative electrode active materials during manufacture, as well as expansion/contraction during repeated charge/discharging cycles when used in a rechargeable secondary battery are described. These copper foils find specific utility as current collectors in rechargeable secondary batteries, particularly in lithium secondary battery with high capacity. Methods of making the copper foils, methods of producing negative electrode for use in lithium secondary battery and lithium secondary battery of high capacity are also described.

Abstract: A semiconductor device with different configurations of gate structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a gate opening on the fin structure, forming a metallic oxide layer within the gate opening, forming a first dielectric layer on the metallic oxide layer, forming a second dielectric layer on the first dielectric layer, forming a work function metal (WFM) layer on the second dielectric layer, and forming a gate metal fill layer on the WFM layer. The forming the first dielectric layer includes depositing an oxide material with an oxygen areal density less than an oxygen areal density of the metallic oxide layer.

Abstract: A semiconductor structure includes a first fin structure and a second fin structure, a first dielectric layer disposed over the first fin structure, a second dielectric layer disposed over the second fin structure, a first gate electrode disposed over the first dielectric layer, and a second gate electrode disposed over the second dielectric layer. A thickness of the first dielectric layer and a thickness of the second dielectric layer are equal. The second fin structure includes an outer region and an inner region, and a Ge concentration in the outer portion is less than Ge concentration in the inner portion.

Abstract: A semiconductor device includes a semiconductor substrate, an interfacial layer formed on the semiconductor substrate, a high-k dielectric layer formed on the interfacial layer, and a conductive gate electrode layer formed on the high-k dielectric layer. At least one of the high-k dielectric layer and the interfacial layer is doped with: a first dopant species, a second dopant species, and a third dopant species. The first dopant species and the second dopant species form a plurality of first dipole elements having a first polarity. The third dopant species forms a plurality of second dipole elements having a second polarity, and the first and second polarities are opposite.

Abstract: A semiconductor device includes a semiconductor fin, an epitaxial region located on a side of the semiconductor fin, a silicide layer disposed on the epitaxial region, a contact plug disposed on the silicide layer and over the epitaxial region, and a self-align contact (SAC) layer disposed on the semiconductor fin. At least a part of the SAC layer is implanted with at least one implantation element. The semiconductor fin is spaced apart from the contact plug by the SAC layer.

Abstract: A semiconductor device includes a channel layer, an interfacial layer, a gate dielectric layer, a gate electrode, dipole elements, and additional elements. The interfacial layer is disposed on the channel layer, and includes an insulating material. The gate dielectric layer is disposed over the interfacial layer such that the channel layer is separated from the gate dielectric layer by the interfacial layer. The gate electrode is disposed on the gate dielectric layer. The dipole elements are present in at least one of the interfacial layer and the gate dielectric layer in a predetermined amount such that the semiconductor device has a predetermined threshold voltage. The additional elements are located at a region where the dipole elements are present so as to reduce interfacial defects caused by the dipole elements. The additional elements are different from the dipole elements. Methods for manufacturing the semiconductor device are also disclosed.

Abstract: A semiconductor structure includes a substrate including a first region and a second region, a first channel layer disposed in the first region and a second channel layer disposed in the second region, a first dielectric layer disposed on the first channel layer and a second dielectric layer disposed on the second channel layer, and a first gate electrode disposed on the first dielectric layer and a second gate electrode disposed on the second dielectric layer. The first channel layer in the first region includes Ge compound of a first Ge concentration, the second channel layer in the second region includes Ge compound of a second Ge concentration. The first Ge concentration in the first channel layer is greater than the second Ge concentration in the second channel layer.

Abstract: Embodiments of the present disclosure provide a method of forming N-type and P-type source/drain features using one patterned mask and one self-aligned mask to increase windows of error tolerance and provide flexibilities for source/drain features of various shapes and/or volumes. In some embodiments, after forming a first type of source/drain features, a self-aligned mask layer is formed over the first type of source/drain features without using photolithography process, thus, avoid damaging the first type of source/drain features in the patterning process.

Abstract: A semiconductor device includes a semiconductor fin, a gate structure, a doped semiconductor layer, and a dielectric structure. The semiconductor fin has a top portion and a lower portion extending from the top portion to a substrate. The gate structure extends across the semiconductor fin. The doped semiconductor layer interfaces the top portion of the semiconductor fin. In a cross-section taken along a lengthwise direction of the gate structure, the doped semiconductor layer has an outer profile conformal to a profile of the top portion of the semiconductor fin.

Abstract: Embodiments of the present disclosure provide a method of forming N-type and P-type source/drain features using one patterned mask and one self-aligned mask to increase windows of error tolerance and provide flexibilities for source/drain features of various shapes and/or volumes. In some embodiments, after forming a first type of source/drain features, a self-aligned mask layer is formed over the first type of source/drain features without using photolithography process, thus, avoid damaging the first type of source/drain features in the patterning process.

Abstract: A semiconductor device includes a semiconductor substrate, a semiconductor fin extending from the semiconductor substrate, a gate structure extending across the semiconductor fin, and source/drain semiconductor layers on opposite sides of the gate structure. The source/drain semiconductor layers each have a first thickness over a top side of the semiconductor fin and a second thickness over a lateral side of the semiconductor fin. The first thickness and the second thickness have a difference smaller than about 20 percent of the first thickness.

Abstract: A semiconductor device with different configurations of gate structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a gate opening on the fin structure, forming an interfacial oxide layer on the fin structure, forming a first dielectric layer over the interfacial oxide layer, forming a dipole layer between the interfacial oxide layer and the first dielectric layer, forming a second dielectric layer on the first dielectric layer, forming a work function metal (WFM) layer on the second dielectric layer, and forming a gate metal fill layer on the WFM layer. The dipole layer includes ions of first and second metals that are different from each other. The first and second metals have electronegativity values greater than an electronegativity value of a metal or a semiconductor of the first dielectric layer.

Abstract: A semiconductor device with different configurations of gate structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a gate opening on the fin structure, forming a metallic oxide layer within the gate opening, forming a first dielectric layer on the metallic oxide layer, forming a second dielectric layer on the first dielectric layer, forming a work function metal (WFM) layer on the second dielectric layer, and forming a gate metal fill layer on the WFM layer. The forming the first dielectric layer includes depositing an oxide material with an oxygen areal density less than an oxygen areal density of the metallic oxide layer.

Abstract: A semiconductor device with different configurations of gate structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a gate opening on the fin structure, forming an interfacial oxide layer on the fin structure, forming a first dielectric layer over the interfacial oxide layer, forming a dipole layer between the interfacial oxide layer and the first dielectric layer, forming a second dielectric layer on the first dielectric layer, forming a work function metal (WFM) layer on the second dielectric layer, and forming a gate metal fill layer on the WFM layer. The dipole layer includes ions of first and second metals that are different from each other. The first and second metals have electronegativity values greater than an electronegativity value of a metal or a semiconductor of the first dielectric layer.

Abstract: A semiconductor device with different configurations of gate structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a gate opening on the fin structure, forming an interfacial oxide layer on the fin structure, forming a first dielectric layer over the interfacial oxide layer, forming a dipole layer between the interfacial oxide layer and the first dielectric layer, forming a second dielectric layer on the first dielectric layer, forming a work function metal (WFM) layer on the second dielectric layer, and forming a gate metal fill layer on the WFM layer. The dipole layer includes ions of first and second metals that are different from each other. The first and second metals have electronegativity values greater than an electronegativity value of a metal or a semiconductor of the first dielectric layer.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first source/drain epitaxial feature formed over a substrate, a second source/drain epitaxial feature formed over the substrate, two or more semiconductor layers disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature, a gate electrode layer surrounding a portion of one of the two or more semiconductor layers, a first dielectric region disposed in the substrate and in contact with a first side of the first source/drain epitaxial feature, and a second dielectric region disposed in the substrate and in contact with a first side of the second source/drain epitaxial feature, the second dielectric region being separated from the first dielectric region by a substrate.

Abstract: A semiconductor device includes a semiconductor substrate, an interfacial layer formed on the semiconductor substrate, a high-k dielectric layer formed on the interfacial layer, and a conductive gate electrode layer formed on the high-k dielectric layer. At least one of the high-k dielectric layer and the interfacial layer is doped with: a first dopant species, a second dopant species, and a third dopant species. The first dopant species and the second dopant species form a plurality of first dipole elements having a first polarity. The third dopant species forms a plurality of second dipole elements having a second polarity, and the first and second polarities are opposite.

Abstract: Embodiments of the present disclosure provide a method of forming N-type and P-type source/drain features using one patterned mask and one self-aligned mask to increase windows of error tolerance and provide flexibilities for source/drain features of various shapes and/or volumes. In some embodiments, after forming a first type of source/drain features, a self-aligned mask layer is formed over the first type of source/drain features without using photolithography process, thus, avoid damaging the first type of source/drain features in the patterning process.

Abstract: The present disclosure describes an inner spacer structure for a semiconductor device and a method for forming the same. The method for forming the inner spacer structure in the semiconductor device can include forming a vertical structure over a substrate, forming a gate structure over a portion of the vertical structure, exposing sidewalls of the portion of the vertical structure, forming multiple spacers over the sidewalls of the portion of the vertical structure, and forming a void in each of the multiple spacers.