Patents by Inventor Yao-Sheng Huang

Yao-Sheng Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190340968
    Abstract: An integrated circuit for driving a display panel and an anti-interference method are provided. The integrated circuit includes a source driving circuit and an anti-interference circuit. The source driving circuit includes a receiving circuit configured to receive an input signal including image data and process the input signal based on at least one operation parameter to generate output data. The anti-interference circuit is coupled to the receiving circuit. The anti-interference circuit determines whether an interference event occurs to the input signal based on the input signal or the output data to obtain a determination result and determines whether to adjust the at least one operation parameter of the receiving circuit according to the determination result.
    Type: Application
    Filed: December 22, 2018
    Publication date: November 7, 2019
    Applicant: Novatek Microelectronics Corp.
    Inventors: Chih-Hao Huang, Wei-Sheng Tseng, Yao-Hung Kuo, Hao-Wei Hung
  • Publication number: 20190341000
    Abstract: An integrated circuit for driving a display panel and an anti-interference method are provided. The integrated circuit includes a source driving circuit and an anti-interference circuit. The source driving circuit includes a receiving circuit configured to receive an input signal including image data and process the input signal based on at least one operation parameter to generate output data. The anti-interference circuit is coupled to the receiving circuit. The anti-interference circuit is configured to adjust the at least one operation parameter of the receiving circuit from at least one normal parameter to at least one anti-interference parameter when an interference event occurs to the input signal. The anti-interference circuit is configured to maintain the at least one operation parameter of the receiving circuit at the at least one normal parameter when the interference event does not occur.
    Type: Application
    Filed: December 22, 2018
    Publication date: November 7, 2019
    Applicant: Novatek Microelectronics Corp.
    Inventors: Wei-Sheng Tseng, Hao-Wei Hung, Chih-Hao Huang, Yao-Hung Kuo
  • Patent number: 10424793
    Abstract: An electrodeposited copper foil of high toughness having a lightness L* value of the deposit side in the range of 36 to 74, the copper foil having a tensile strength in the range of 40 to 70 kg/mm2, and a weight deviation of less than 3%. The electrodeposited copper foils are particularly useful as current collectors for anode components of rechargeable secondary batteries and tend not to form wrinkles during charge-discharge cycles of the battery and are resistant to fracture during pressing of the anode active materials onto the copper foil. Secondary batteries and methods of manufacture are also described.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: September 24, 2019
    Assignee: CHANG CHUN PETROCHEMICAL CO., LTD.
    Inventors: Kuei-Sen Cheng, Huei-Fang Huang, Yao-Sheng Lai, Jui-Chang Chou
  • Publication number: 20190173091
    Abstract: Electrodeposited copper foils having adequate puncture strength to withstand both pressure application during consolidation with negative electrode active materials during manufacture, as well as expansion/contraction during repeated charge/discharging cycles when used in a rechargeable secondary battery are described. These copper foils find specific utility as current collectors in rechargeable secondary batteries, particularly in lithium secondary battery with high capacity. Methods of making the copper foils, methods of producing negative electrode for use in lithium secondary battery and lithium secondary battery of high capacity are also described.
    Type: Application
    Filed: December 17, 2018
    Publication date: June 6, 2019
    Applicant: CHANG CHUN PETROCHEMICAL CO., LTD.
    Inventors: Huei-Fang HUANG, Kuei-Sen CHENG, Yao-Sheng LAI, Jui-Chang CHOU
  • Publication number: 20190148736
    Abstract: An electrodeposited copper foil of high toughness having a lightness L* value of the deposit side in the range of 36 to 74, the copper foil having a tensile strength in the range of 40 to 70 kg/mm2, and a weight deviation of less than 3%. The electrodeposited copper foils are particularly useful as current collectors for anode components of rechargeable secondary batteries and tend not to form wrinkles during charge-discharge cycles of the battery and are resistant to fracture during pressing of the anode active materials onto the copper foil. Secondary batteries and methods of manufacture are also described.
    Type: Application
    Filed: November 14, 2017
    Publication date: May 16, 2019
    Applicant: CHANG CHUN PETROCHEMICAL CO., LTD.
    Inventors: Kuei-Sen CHENG, Huei-Fang HUANG, Yao-Sheng LAI, Jui-Chang CHOU
  • Patent number: 8969869
    Abstract: An integrated circuit wafer and integrated circuit dice are provided. The integrated circuit wafer includes a wafer substrate, a plurality of integrated circuits, a plurality of test-keys, an isolation film, and a plurality of ditches. The integrated circuits are disposed on the wafer substrate in matrix. The test-keys are respectively disposed between the adjacent integrated circuits. The isolation film covers at least one side of the integrated circuits on the wafer substrate. The ditches extend downwardly from the surface of the isolation film and are disposed between the integrated circuit and the adjacent test-key. The integrated circuit die includes a wafer substrate, an integrated circuit disposed on the wafer substrate, and an isolation film covering at least one side of the integrated circuit on the wafer substrate, wherein the side walls of the wafer substrate and the isolation film are respectively smooth walls. The side wall of the wafer substrate is substantially vertical.
    Type: Grant
    Filed: November 11, 2010
    Date of Patent: March 3, 2015
    Assignee: Raydium Semiconductor Corporation
    Inventor: Yao-Sheng Huang
  • Publication number: 20110272799
    Abstract: An IC chip and an IC chip manufacturing method thereof are provided. The IC chip has a chip body and at least one bump. The chip body has at least one conducting area on its surface. The bump is formed on the conducting area of the chip body. The bump includes a plurality of protrusions and at least one conducting material. The protrusions protrude out of the conducting area and are spaced apart from each other. The conducting material covers the protrusions and electrically connects the conducting area. The method includes: (A) providing a chip body having a conducting area on its surface; (B) forming a plurality of protrusions on the chip body, wherein the protrusions protrude out of the conducting area and are spaced apart from each other; and (C) forming at least one conducting material, wherein the conducting material covers the protrusions and electrically connects the conducting area.
    Type: Application
    Filed: April 19, 2011
    Publication date: November 10, 2011
    Inventor: Yao-Sheng Huang
  • Publication number: 20110256690
    Abstract: An integrated circuit wafer dicing method is provided. The method includes forming a plurality of integrated circuits on a wafer substrate, forming a patterned protective layer on the integrated circuits, and etching through the wafer substrate to form a plurality of integrated circuit dies by using the patterned protective layer as a mask. The patterned protective layer is preferably a patterned photoresist layer. The step of forming the patterned protective layer includes covering the wafer substrate with a photoresist layer, exposing the photoresist layer by using a photomask, and developing the exposed photoresist layer to form the patterned protective layer. The etching process can be dry etching or wet etching.
    Type: Application
    Filed: April 19, 2011
    Publication date: October 20, 2011
    Inventor: Yao-Sheng Huang
  • Publication number: 20110114950
    Abstract: An integrated circuit wafer and integrated circuit dice are provided. The integrated circuit wafer includes a wafer substrate, a plurality of integrated circuits, a plurality of test-keys, an isolation film, and a plurality of ditches. The integrated circuits are disposed on the wafer substrate in matrix. The test-keys are respectively disposed between the adjacent integrated circuits. The isolation film covers at least one side of the integrated circuits on the wafer substrate. The ditches extend downwardly from the surface of the isolation film and are disposed between the integrated circuit and the adjacent test-key. The integrated circuit die includes a wafer substrate, an integrated circuit disposed on the wafer substrate, and an isolation film covering at least one side of the integrated circuit on the wafer substrate, wherein the side walls of the wafer substrate and the isolation film are respectively smooth walls. The side wall of the wafer substrate is substantially vertical.
    Type: Application
    Filed: November 11, 2010
    Publication date: May 19, 2011
    Inventor: Yao-Sheng Huang
  • Publication number: 20110103034
    Abstract: An electronic chip includes a plurality of conducting pins and a plurality of insulating blocks. The conducting pins are disposed on an outer side of the electronic chip to provide electrical connections between the electronic chip and an external circuit. Each of the insulating blocks is disposed between two adjacent conducting pins.
    Type: Application
    Filed: November 4, 2010
    Publication date: May 5, 2011
    Inventors: Yao-Sheng Huang, Ching-Jung Yang
  • Publication number: 20050158944
    Abstract: A mixed-mode process introduces a hard mask layer. Due to the introduced hard mask layer made of non-resist material formed over devices, performance of a formed capacitor is protected from effects of an implantation process such as source/drain implantation. A self-aligned silicide (salicide) process for a MOSFET transistor can also be performed. Thus, production efficiency and performance of an IC product formed by the mixed-mode process can be improved. Moreover, the number of required fabrication steps is reduced and cost savings can be realized.
    Type: Application
    Filed: January 15, 2004
    Publication date: July 21, 2005
    Inventors: Yao-Sheng Huang, Hui-Lun Chen, Ming-Yi Lee
  • Patent number: 6916700
    Abstract: A mixed-mode process introduces a hard mask layer. Due to the introduced hard mask layer made of non-resist material formed over devices, performance of a formed capacitor is protected from effects of an implantation process such as source/drain implantation. A self-aligned silicide (salicide) process for a MOSFET transistor can also be performed. Thus, production efficiency and performance of an IC product formed by the mixed-mode process can be improved. Moreover, the number of required fabrication steps is reduced and cost savings can be realized.
    Type: Grant
    Filed: January 15, 2004
    Date of Patent: July 12, 2005
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yao-Sheng Huang, Hui-Lun Chen, Ming-Yi Lee