Abstract: A sensing structure and a method of fabricating a sensing structure for a compressive-type pressure sensor. The method comprises the steps of providing an elastic micropatterned substrate defining a plurality of 3-dimensional microstructures, each microstructure comprising a tip portion pointing away from the substrate in a first direction; forming a conductive film on the elastic micropatterned substrate such that the 3-dimensional microstructures are substantially covered by the conductive film; and forming cracks in the conductive film in areas on 3-dimensional microstructures.

Abstract: The present disclosure describes an example method for cell placement in an integrated circuit (IC) layout design. The method includes defining a layout unit for a circuit implementation and arranging multiple layout units into a layout cell. The method also includes editing the layout cell to connect a first set of the layout units to be representative of the circuit implementation and to connect a second set of the layout units to be representative of a non-functional circuit. Further, the method includes inserting one or more dummy fill structures in areas of the layout cell unoccupied by the first and second sets of layout units.

Abstract: The present disclosure describes an example method for cell placement in an integrated circuit (IC) layout design. The method includes defining a layout unit for a circuit implementation and arranging multiple layout units into a layout cell. The method also includes editing the layout cell to connect a first set of the layout units to be representative of the circuit implementation and to connect a second set of the layout units to be representative of a non-functional circuit. Further, the method includes inserting one or more dummy fill structures in areas of the layout cell unoccupied by the first and second sets of layout units.

Abstract: The present disclosure describes an example method for cell placement in an integrated circuit (IC) layout design. The method includes defining a layout unit for a circuit implementation and arranging multiple layout units into a layout cell. The method also includes editing the layout cell to connect a first set of the layout units to be representative of the circuit implementation and to connect a second set of the layout units to be representative of a non-functional circuit. Further, the method includes inserting one or more dummy fill structures in areas of the layout cell unoccupied by the first and second sets of layout units.

Abstract: The present disclosure describes an example method for cell placement in an integrated circuit (IC) layout design. The method includes defining a layout unit for a circuit implementation and arranging multiple layout units into a layout cell. The method also includes editing the layout cell to connect a first set of the layout units to be representative of the circuit implementation and to connect a second set of the layout units to be representative of a non-functional circuit. Further, the method includes inserting one or more dummy fill structures in areas of the layout cell unoccupied by the first and second sets of layout units.

Abstract: The present disclosure describes an example method for cell placement in an integrated circuit (IC) layout design. The method includes defining a layout unit for a circuit implementation and arranging multiple layout units into a layout cell. The method also includes editing the layout cell to connect a first set of the layout units to be representative of the circuit implementation and to connect a second set of the layout units to be representative of a non-functional circuit. Further, the method includes inserting one or more dummy fill structures in areas of the layout cell unoccupied by the first and second sets of layout units.

Abstract: The present disclosure describes an example method for cell placement in an integrated circuit (IC) layout design. The method includes defining a layout unit for a circuit implementation and arranging multiple layout units into a layout cell. The method also includes editing the layout cell to connect a first set of the layout units to be representative of the circuit implementation and to connect a second set of the layout units to be representative of a non-functional circuit. Further, the method includes inserting one or more dummy fill structures in areas of the layout cell unoccupied by the first and second sets of layout units.

Abstract: A package assembly includes a main body, a power module and replaceable top cover. The main body has a hollow part. The power module is disposed within a hollow part of the main body and located beside the bottom part of the main body. At least one first pin is disposed on a surface of the power module. The at least one first pin is accommodated within the hollow part of the main body and partially protruded out of a first open end of the hollow part near a top part of the main body. The top cover is disposed in the hollow part of the main body, and includes at least one first opening corresponding to the at least one first pin. The at least one first pin is penetrated through the corresponding first opening and exposed outside the first open end of the hollow part.

Abstract: A package assembly includes a housing frame, a power module, a first heat dissipating module and a second heat dissipating module. The housing frame is fixed on the first heat dissipating module. The power module is disposed within a hollow part of the housing frame, and covers a first open end of the hollow part. The power module includes a first surface, a second surface and at least one pin. The first surface has a periphery region and a middle region. The second surface is attached on the first heat dissipating module. The at least one pin is disposed on the periphery region. The at least one pin is penetrated through the corresponding opening and partially exposed outside the housing frame. The second heat dissipating module is disposed within the hollow part and attached on the middle region of the first surface of the power module.

Abstract: A package assembly includes a housing frame, a power module, a first heat dissipating module and a second heat dissipating module. The housing frame is fixed on the first heat dissipating module. The power module is disposed within a hollow part of the housing frame, and covers a first open end of the hollow part. The power module includes a first surface, a second surface and at least one pin. The first surface has a periphery region and a middle region. The second surface is attached on the first heat dissipating module. The at least one pin is disposed on the periphery region. The at least one pin is penetrated through the corresponding opening and partially exposed outside the housing frame. The second heat dissipating module is disposed within the hollow part and attached on the middle region of the first surface of the power module.

Abstract: A package assembly includes a main body, a power module and replaceable top cover. The main body has a hollow part. The power module is disposed within a hollow part of the main body and located beside the bottom part of the main body. At least one first pin is disposed on a surface of the power module. The at least one first pin is accommodated within the hollow part of the main body and partially protruded out of a first open end of the hollow part near a top part of the main body. The top cover is disposed in the hollow part of the main body, and includes at least one first opening corresponding to the at least one first pin. The at least one first pin is penetrated through the corresponding first opening and exposed outside the first open end of the hollow part.

Abstract: Apparatus and method for electronically screening abnormal glow curves of thermoluminescenct materials such as LiF:Mg,Ti in routine dosimetry, wherein glow curves with abnormal patterns are identified by examining a few key features from which information about background and thermoluminescent (TL) signals can be extracted. By analyzing the records of quality control (QC) cards that are in the same group as field cards, dosimeter- and reader-dictated parameters, such as the peak location, are automatically determined, thus eliminating the need for any prior knowledge of those conditions required for reference determination. The apparatus and method are applicable to dose levels down to at least 50 .mu.Sv.