Abstract: A semiconductor structure includes a substrate, and an active device and a passive device over the substrate. The active device is disposed in a first region of the substrate, and the passive device is disposed in a second region of the substrate. The semiconductor structure further includes a shielding structure and a passivation layer. The shielding structure includes a barrier layer and a ceiling layer. The barrier layer is on the passive device and the active device, and the ceiling layer is on the barrier layer. The passivation layer is under the barrier layer and covers a top surface of the passive device. An air cavity is defined by sidewalls of the barrier layer, a bottom surface of the ceiling layer, and the substrate.

Abstract: A semiconductor structure includes a substrate, and an active device and a passive device over the substrate. The active device is disposed in a first region of the substrate, and the passive device is disposed in a second region of the substrate. The semiconductor structure further includes a shielding structure and a passivation layer. The shielding structure includes a barrier layer and a ceiling layer. The barrier layer is on the passive device and the active device, and the ceiling layer is on the barrier layer. The passivation layer is under the barrier layer and covers a top surface of the passive device. An air cavity is defined by sidewalls of the barrier layer, a bottom surface of the ceiling layer, and the substrate.

Abstract: A semiconductor structure includes a substrate, a passive device and an active device over the substrate. The active device is formed in the first region of the substrate, and the passive device is formed in the second region of the substrate. The semiconductor structure further includes a passivation layer that covers the top surface of the passive device. The passivation layer has an opening that exposes the active device.

Abstract: A semiconductor structure includes a substrate, a passive device and an active device over the substrate. The active device is formed in the first region of the substrate, and the passive device is formed in the second region of the substrate. The semiconductor structure further includes a passivation layer that covers the top surface of the passive device. The passivation layer has an opening that exposes the active device.

Abstract: The present invention uses a double exposure and double etching method to improve critical dimension uniformity. A coating layer is formed on a wafer that includes a first area and a second area. The first area and the second area are separately patterned with different processing conditions. By means of this two-stage patterning, the CD uniformity between wafer center and wafer edge is successfully improved over the conventional single-stage patterning process. The fabrication yield is thus enhanced.

Abstract: A method of manufacturing a contact is disclosed. A substrate is provided, and a first dielectric layer and a metal layer are formed thereon in sequence. A second dielectric layer is formed on the metal layer and the first dielectric layer. A bottom contact is formed in the second dielectric layer to electrically connect to the metal layer. A node contact is formed in the first and second dielectric layers. A capacitor is formed on the dielectric layer to electrically connect to the node contact, and a middle contact is formed on the second dielectric layer to electrically connect to the bottom contact. A third dielectric layer is formed on the capacitor, the middle contact and the second dielectric layer. A top contact is formed in the third dielectric layer to electrically connect to the middle contact.

Abstract: A method of manufacturing a contact is disclosed. A substrate is provided, and a first dielectric layer and a metal layer are formed thereon in sequence. A second dielectric layer is formed on the metal layer and the first dielectric layer. A bottom contact is formed in the second dielectric layer to electrically connect to the metal layer. A node contact is formed in the first and second dielectric layers. A capacitor is formed on the dielectric layer to electrically connect to the node contact, and a middle contact is formed on the second dielectric layer to electrically connect to the bottom contact. A third dielectric layer is formed on the capacitor, the middle contact and the second dielectric layer. A top contact is formed in the third dielectric layer to electrically connect to the middle contact.

Abstract: The present invention uses a double exposure and double etching method to improve critical dimension uniformity. A coating layer is formed on a wafer that includes a first area and a second area. The first area and the second area are separately patterned with different processing conditions. By means of this two-stage patterning, the CD uniformity between wafer center and wafer edge is successfully improved over the conventional single-stage patterning process. The fabrication yield is thus enhanced.