Abstract: A Green NAND SSD (GNSD) controller receives reads and writes from a host and writes to flash memory. A SSD DRAM has a DRAM Translation Layer (ETL) with buffers managed by the GNSD controller. The GNSD controller performs deduplication, compression, encryption, high-level error-correction, and grouping of host data writes, and manages mapping tables to store host write data in the SSD DRAM to reduce writes to flash memory. The GNSD controller categorizes host writes as data types for paging files, temporary files, meta-data, and user data files, using address ranges and file extensions read from meta-data tables. Paging files and temporary files are optionally written to flash. Full-page and partial-page data are grouped into multi-page meta-pages by data type before storage by the GNSD controller. Status bits include two overwrite bits indicating frequently-written data that is retained in the SSD DRAM rather than being flushed to flash and re-allocated.

Abstract: A GNSD Driver coupled to host DRAM, and having a memory manager, a data grouper engine, a data ungrouper engine, a power manager, and a flush/resume manager. The GNSD driver is coupled to a GNSD application, and the host DRAM to a Non-Volatile Memory Device. The GNSD Driver further includes a compression/decompression engine, a de-duplication engine, an encryption/decryption engine, or a high-level error correction code engine. The encryption/decryption engine encrypts according to DES or AES. A method of operating a GNSD Driver and a GNSD application coupled to DRAM of a host, includes coupling: Configuration and Register O/S Settings to the host and the GNSD Application; a data grouper and data ungrouper to the host DRAM and to Upper and a Lower Filter; a power manager and a memory manager to the host; a flush/resume manager to the DRAM; and the DRAM to an SEED SSD.

Abstract: A GNSD Driver coupled to host DRAM, and having a memory manager, a data grouper engine, a data ungrouper engine, a power manager, and a flush/resume manager. The GNSD driver is coupled to a GNSD application, and the host DRAM to a Non-Volatile Memory Device. The GNSD Driver further includes a compression/decompression engine, a de-duplication engine, an encryption/decryption engine, or a high-level error correction code engine. The encryption/decryption engine encrypts according to DES or AES. A method of operating a GNSD Driver and a GNSD application coupled to DRAM of a host, includes coupling: Configuration and Register O/S Settings to the host and the GNSD Application; a data grouper and data ungrouper to the host DRAM and to Upper and a Lower Filter; a power manager and a memory manager to the host; a flush/resume manager to the DRAM; and the DRAM to an SEED SSD.

Abstract: A GNSD (Green NAND Solid State Drive) Driver coupled to host DRAM, and having a memory manager, a data grouper engine, a data ungrouper engine, a power manager, and a flush/resume manager. The GNSD driver is coupled to a GNSD application, and the host DRAM to a Non-Volatile Memory Device. The GNSD Driver further includes a compression/decompression engine, a de-duplication engine, an encryption/decryption engine, or a high-level error correction code engine. The encryption/decryption engine encrypts according to DES (Data Encryption Standard) or AES (Advanced Encryption Standard). A method of operating a GNSD Driver and a GNSD application coupled to DRAM of a host, includes coupling: Configuration and Register O/S Settings to the host and the GNSD Application; a data grouper and data ungrouper to the host DRAM and to Upper and a Lower Filter; a power manager and a memory manager to the host; a flush/resume manager to the DRAM; and the DRAM to an (Super Enhanced Endurance Device) SEED SSD (Solid State Drive).

Abstract: A GNSD Driver coupled to host DRAM, and having a memory manager, a data grouper engine, a data ungrouper engine, a power manager, and a flush/resume manager. The GNSD driver is coupled to a GNSD application, and the host DRAM to a Non-Volatile Memory Device. The GNSD Driver further includes a compression/decompression engine, a de-duplication engine, an encryption/decryption engine, or a high-level error correction code engine. The encryption/decryption engine encrypts according to DES or AES. A method of operating a GNSD Driver and a GNSD application coupled to DRAM of a host, includes coupling: Configuration and Register O/S Settings to the host and the GNSD Application; a data grouper and data ungrouper to the host DRAM and to Upper and a Lower Filter; a power manager and a memory manager to the host; a flush/resume manager to the DRAM; and the DRAM to an SEED SSD.

Abstract: An retention flash controller reads assigned-level bits from a bad block/erase count table or from a page status table that indicate when flash memory cells operate as Triple-Level-Cell (TLC), Multi-Level-Cell (MLC), or Single-Level-Cell (SLC). Pages that fail as TLC or MLC are downgraded for use as SLC pages by changing the assigned-level bits. The level bits adjust truth tables used by translation logic that receives inputs from voltage comparators reading a bit line. The range of voltages for each logic level may be adjusted by the truth tables or by programmable registers. The programming voltage or programming pulses may be adjusted to increase endurance and the number of permitted program-erase cycles while reducing retention times before a refresh is needed of the flash cells. Mixed configurations of flash memory have MLC blocks and MLC as SLC blocks, or other combinations.

Abstract: An retention flash controller reads assigned-level bits from a bad block/erase count table or from a page status table that indicate when flash memory cells operate as Triple-Level-Cell (TLC), Multi-Level-Cell (MLC), or Single-Level-Cell (SLC). Pages that fail as TLC or MLC are downgraded for use as SLC pages by changing the assigned-level bits. The level bits adjust truth tables used by translation logic that receives inputs from voltage comparators reading a bit line. The range of voltages for each logic level may be adjusted by the truth tables or by programmable registers. The programming voltage or programming pulses may be adjusted to increase endurance and the number of permitted program-erase cycles while reducing retention times before a refresh is needed of the flash cells. Mixed configurations of flash memory have MLC blocks and MLC as SLC blocks, or other combinations.

Abstract: The present invention relates to an algorithm of flash memory capable of quickly building a mapping table and preventing disorder of data due to abnormal disconnection and a control system thereof, wherein pages of a physical block store data of the mapping table of logical block addresses and corresponding physical block addresses. A set of ECC data are used for protection. When the host computer is normally turned on, data of the mapping table are directly stored into a buffer so that the control device can read. The system can quickly build the mapping table to save the time and operation of turning on without the need of a scanning procedure. If an error of the mapping table due to improper operation occurs, the previous mapping table can be retraced to restore the system to the normal state.

Abstract: The present invention relates to an algorithm of flash memory capable of quickly building a mapping table and preventing disorder of data due to abnormal disconnection and a control system thereof, wherein pages of a physical block store data of the mapping table of logical block addresses and corresponding physical block addresses. A set of ECC data are used for protection. When the host computer is normally turned on, data of the mapping table are directly stored into a buffer so that the control device can read. The system can quickly build the mapping table to save the time and operation of turning on without the need of a scanning procedure. If an error of the mapping table due to improper operation occurs, the previous mapping table can be retraced to restore the system to the normal state.