Patents by Inventor Yao-Tsung Huang

Yao-Tsung Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240161343
    Abstract: An image processing method includes following operations: receiving, by a processor, an input image from a camera; performing, by the processor, a top-view calibration process to generate a top-view calibrated image according to the input image; performing, by the processor, an object extraction process on the top-view calibrated image to generate at least one target object frame; performing, by the processer, a centering process on the at least one target object frame to generate a centered image; and outputting, by the processor, the centered image for a display panel to display.
    Type: Application
    Filed: June 7, 2023
    Publication date: May 16, 2024
    Inventors: Yi-Hsuan HUANG, Yao-Jia KUO, Yu-Chi TSAI, Wen-Tsung HUANG
  • Publication number: 20240096860
    Abstract: A multi-die package on package includes a bottom package having a first device die and a second device die. A top package including a memory die is stacked on the bottom package.
    Type: Application
    Filed: August 14, 2023
    Publication date: March 21, 2024
    Applicant: MEDIATEK INC.
    Inventors: Tai-Hao Peng, Yao-Tsung Huang
  • Publication number: 20230387025
    Abstract: A semiconductor device includes a first layer structure, a second layer structure, a bridge die, a first SoC and a second SoC. The bridge die is disposed between the first layer structure and the second layer structure. The first SoC and the second SoC are disposed on the second layer structure. The first SoC and the second SoC are electrically connected through the bridge die.
    Type: Application
    Filed: March 28, 2023
    Publication date: November 30, 2023
    Inventors: Tai-Hao PENG, Yao-Tsung HUANG
  • Publication number: 20230260977
    Abstract: Various embodiments of a 3DIC die package, including trench capacitors integrated with IC dies, are disclosed. A 3DIC die package includes a first IC die and a second IC die disposed on the first IC die. The first IC die includes a substrate having a first surface and a second surface opposite to the first surface, a first active device disposed on the first surface of the substrate, and a passive device disposed on the second surface of the substrate. The passive device includes a plurality of trenches disposed in the substrate and through the second surface of the substrate, first and second conductive layers disposed in the plurality of trenches and on the second surface of the substrate, and a first dielectric layer disposed between the first and second conductive layers. The second IC die includes a second active device.
    Type: Application
    Filed: October 7, 2022
    Publication date: August 17, 2023
    Applicant: MediaTek Inc.
    Inventors: Hsiao-Yun CHEN, Chi-Hung HUANG, Yao-Tsung HUANG, Cheng-Jyi CHANG, Sheng Chieh CHANG
  • Publication number: 20230125239
    Abstract: A semiconductor package structure includes a first redistribution layer, a first semiconductor die, a second through via, a molding material, a second semiconductor die, and a second redistribution layer. The first semiconductor die is disposed over the first redistribution layer and includes a first through via having a first width. The second through via is adjacent to the first semiconductor die and has a second width. The second width is greater than the first width. The molding material surrounds the first semiconductor die and the second through via. The second semiconductor die is disposed over the molding material and is electrically coupled to the first through via and the second through via. The second redistribution layer is disposed over the second semiconductor die.
    Type: Application
    Filed: September 22, 2022
    Publication date: April 27, 2023
    Inventors: Hsiao-Yun CHEN, Yao-Tsung HUANG, Cheng-Jyi CHANG
  • Publication number: 20220406921
    Abstract: A semiconductor chip includes a substrate and a transistor. The transistor is formed on the substrate and includes an insulation layer and a fin. The fin includes a base portion and a protrusion connected with the base portion, wherein the protrusion is projected with respect to an upper surface of the base portion and has a recess recessed with respect to the upper surface.
    Type: Application
    Filed: August 22, 2022
    Publication date: December 22, 2022
    Inventors: Cheng-Tien WAN, Yao-Tsung HUANG, Yun-San HUANG, Ming-Cheng LEE, Wei-Che HUANG
  • Patent number: 11450756
    Abstract: A semiconductor chip includes a substrate and a transistor. The transistor is formed on the substrate and includes an insulation layer and a fin. The fin includes a base portion and a protrusion connected with the base portion, wherein the protrusion is projected with respect to an upper surface of the base portion and has a recess recessed with respect to the upper surface.
    Type: Grant
    Filed: August 25, 2020
    Date of Patent: September 20, 2022
    Assignee: MEDIATEK INC.
    Inventors: Cheng-Tien Wan, Yao-Tsung Huang, Yun-San Huang, Ming-Cheng Lee, Wei-Che Huang
  • Publication number: 20200388700
    Abstract: A semiconductor chip includes a substrate and a transistor. The transistor is formed on the substrate and includes an insulation layer and a fin. The fin includes a base portion and a protrusion connected with the base portion, wherein the protrusion is projected with respect to an upper surface of the base portion and has a recess recessed with respect to the upper surface.
    Type: Application
    Filed: August 25, 2020
    Publication date: December 10, 2020
    Inventors: Cheng-Tien WAN, Yao-Tsung HUANG, Yun-San HUANG, Ming-Cheng LEE, Wei-Che HUANG
  • Patent number: 10790380
    Abstract: A semiconductor chip includes a substrate and a transistor. The transistor is formed on the substrate and includes an insulation layer and a fin. The fin includes a base portion and a protrusion connected with the base portion, wherein the protrusion is projected with respect to an upper surface of the base portion and has a recess recessed with respect to the upper surface.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: September 29, 2020
    Assignee: MEDIATEK INC.
    Inventors: Cheng-Tien Wan, Yao-Tsung Huang, Yun-San Huang, Ming-Cheng Lee, Wei-Che Huang
  • Publication number: 20190123176
    Abstract: A semiconductor chip includes a substrate and a transistor. The transistor is formed on the substrate and includes an insulation layer and a fin. The fin includes a base portion and a protrusion connected with the base portion, wherein the protrusion is projected with respect to an upper surface of the base portion and has a recess recessed with respect to the upper surface.
    Type: Application
    Filed: September 5, 2018
    Publication date: April 25, 2019
    Inventors: Cheng-Tien WAN, Yao-Tsung HUANG, Yun-San HUANG, Ming-Cheng LEE, Wei-Che HUANG
  • Patent number: 9887290
    Abstract: A method includes forming a gate stack over a semiconductor region, and recessing the semiconductor region to form a recess adjacent the gate stack. A silicon-containing semiconductor region is epitaxially grown in the recess to form a source/drain stressor. Arsenic is in-situ doped during the step of epitaxially growing the silicon-containing semiconductor region.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: February 6, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ji-Yin Tsai, Yao-Tsung Huang, Chih-Hsin Ko, Clement Hsingjen Wann
  • Patent number: 9508849
    Abstract: A device including a silicon substrate, a silicon germanium layer, a silicon layer, a gate stack, and silicon-containing stressors is provided. In an embodiment, the silicon germanium layer is disposed over a silicon substrate and relaxed while the silicon layer is disposed over the silicon germanium layer and un-relaxed. The silicon layer may be free from germanium. The gate stack is of an n-type metal-oxide-semiconductor (NMOS) field-effect transistor (FET) and disposed over the silicon layer and the silicon germanium layer. A portion of the silicon layer forms a channel region of the NMOS FET. The silicon-containing stressors are formed in recesses in the silicon layer and have a lattice constant smaller than a lattice constant of the silicon germanium layer.
    Type: Grant
    Filed: November 12, 2013
    Date of Patent: November 29, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Clement Hsingjen Wann, Chih-Hsin Ko, Yao-Tsung Huang, Cheng-Ying Huang
  • Publication number: 20160197071
    Abstract: The invention provides an integrated circuit device. The integrated circuit device includes a semiconductor substrate. An isolation structure is positioned in the semiconductor substrate. A first electrode and a second electrode are positioned on the semiconductor substrate and coupled to different voltage supplies. The first electrode laterally or parallelly overlaps the second electrode. The first electrode and the second electrode vertically overlap the isolation structure. As a result, leakage current is mitigated or eliminated so that the reliability and performance of the integrated circuit device are improved.
    Type: Application
    Filed: September 22, 2015
    Publication date: July 7, 2016
    Inventors: Chao-Yang YEH, Yi-Feng CHEN, Jia-Wei FANG, Yao-Tsung HUANG, Ming-Cheng LEE
  • Publication number: 20150137198
    Abstract: A method includes forming a gate stack over a semiconductor region, and recessing the semiconductor region to form a recess adjacent the gate stack. A silicon-containing semiconductor region is epitaxially grown in the recess to form a source/drain stressor. Arsenic is in-situ doped during the step of epitaxially growing the silicon-containing semiconductor region.
    Type: Application
    Filed: January 29, 2015
    Publication date: May 21, 2015
    Inventors: Ji-Yin Tsai, Yao-Tsung Huang, Chih-Hsin Ko, Clement Hsingjen Wann
  • Patent number: 9034102
    Abstract: A method of fabricating a hybrid orientation substrate is described. A silicon substrate with a first orientation having a silicon layer with a second orientation directly thereon is provided, and then a stress layer is formed on the silicon layer. A trench is formed between a first portion and a second portion of the silicon layer through the stress layer and into the substrate. The first portion of the silicon layer is amorphized. A SPE process is performed to recrystallize the amorphized first portion of the silicon layer to be a recrystallized layer with the first orientation. An annealing process is performed at a temperature lower than 1200° C. to convert a surface layer of the second portion of the silicon layer to a strained layer. The trench is filled with an insulating material after the SPE process or the annealing process, and the stress layer is removed.
    Type: Grant
    Filed: March 29, 2007
    Date of Patent: May 19, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yao-Tsung Huang, Chien-Ting Lin, Che-Hua Hsu, Guang-Hwa Ma
  • Patent number: 8962400
    Abstract: A method includes forming a gate stack over a semiconductor region, and recessing the semiconductor region to form a recess adjacent the gate stack. A silicon-containing semiconductor region is epitaxially grown in the recess to form a source/drain stressor. Arsenic is in-situ doped during the step of epitaxially growing the silicon-containing semiconductor region.
    Type: Grant
    Filed: July 7, 2011
    Date of Patent: February 24, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ji-Yin Tsai, Yao-Tsung Huang, Chih-Hsin Ko, Clement Hsingjen Wann
  • Publication number: 20140312431
    Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a channel region in a workpiece, and forming a source or drain region proximate the channel region. The source or drain region includes a contact resistance-lowering material layer comprising SiP, SiAs, or a silicide. The source or drain region also includes a channel-stressing material layer comprising SiCP or SiCAs.
    Type: Application
    Filed: July 2, 2014
    Publication date: October 23, 2014
    Inventors: Ji-Yin Tsai, Yao-Tsung Huang, Chih-Hsin Ko, Clement Wann
  • Patent number: 8866188
    Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a channel region in a workpiece, and forming a source or drain region proximate the channel region. The source or drain region includes a contact resistance-lowering material layer comprising SiP, SiAs, or a silicide. The source or drain region also includes a channel-stressing material layer comprising SiCP or SiCAs.
    Type: Grant
    Filed: July 2, 2014
    Date of Patent: October 21, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ji-Yin Tsai, Yao-Tsung Huang, Chih-Hsin Ko, Clement Wann
  • Patent number: 8785285
    Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a channel region in a workpiece, and forming a source or drain region proximate the channel region. The source or drain region includes a contact resistance-lowering material layer comprising SiP, SiAs, or a silicide. The source or drain region also includes a channel-stressing material layer comprising SiCP or SiCAs.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: July 22, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ji-Yin Tsai, Yao-Tsung Huang, Chih-Hsin Ko, Clement Hsingjen Wann
  • Publication number: 20140138742
    Abstract: A device including a silicon substrate, a silicon germanium layer, a silicon layer, a gate stack, and silicon-containing stressors is provided. In an embodiment, the silicon germanium layer is disposed over a silicon substrate and relaxed while the silicon layer is disposed over the silicon germanium layer and un-relaxed. The silicon layer may be free from germanium. The gate stack is of an n-type metal-oxide-semiconductor (NMOS) field-effect transistor (FET) and disposed over the silicon layer and the silicon germanium layer. A portion of the silicon layer forms a channel region of the NMOS FET. The silicon-containing stressors are formed in recesses in the silicon layer and have a lattice constant smaller than a lattice constant of the silicon germanium layer.
    Type: Application
    Filed: November 12, 2013
    Publication date: May 22, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Clement Hsingjen Wann, Chih-Hsin Ko, Yao-Tsung Huang, Cheng-Ying Huang