Patents by Inventor Yao-Wen Hsu

Yao-Wen Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11887896
    Abstract: Semiconductor devices and methods which utilize a treatment process of a bottom anti-reflective layer are provided. The treatment process may be a physical treatment process in which material is added in order to fill holes and pores within the material of the bottom anti-reflective layer or else the treatment process may be a chemical treatment process in which a chemical reaction is used to form a protective layer. By treating the bottom anti-reflective layer the diffusion of subsequently applied chemicals is reduced or eliminated, thereby helping to prevent defects that arise from such diffusion.
    Type: Grant
    Filed: June 13, 2022
    Date of Patent: January 30, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yao-Wen Hsu, Ming-Chi Huang, Ying-Liang Chuang
  • Publication number: 20240006295
    Abstract: A manufacturing method of electronic components includes the steps of: providing an insulating layer including a first region and a second region; providing a first metal layer disposed in the first region of the insulating layer; providing a second metal layer disposed on the first metal layer; providing a metal line in the second region of the insulating layer, wherein the metal line is electrically connected to the first metal layer; and removing the metal line to form an electronic component, wherein the electronic component includes the insulating layer; and a first metal bump disposed on the insulating layer and including: the first metal layer disposed on the insulating layer; and the second metal layer disposed on the first metal layer.
    Type: Application
    Filed: September 13, 2023
    Publication date: January 4, 2024
    Inventors: Chung-Chun CHENG, Kuang-Ming FAN, Yao-Wen HSU
  • Patent number: 11798875
    Abstract: An electronic component includes: an insulating layer; and a first metal bump disposed on the insulating layer and provided with: a first metal layer disposed on the insulating layer; and a second metal layer disposed on the first metal layer, wherein, in a cross-sectional view of the electronic component, the first metal layer has a first width, the second metal layer has a second width, and the first width is smaller than the second width.
    Type: Grant
    Filed: November 24, 2021
    Date of Patent: October 24, 2023
    Assignee: INNOLUX CORPORATION
    Inventors: Chung-Chun Cheng, Kuang-Ming Fan, Yao-Wen Hsu
  • Patent number: 11682549
    Abstract: A method comprises depositing a mask layer on a front-side surface of a wafer, wherein a portion of the wafer has a first resistivity; with the mask layer in place, performing an ion implantation process on a backside surface of the wafer to implant a resistivity reduction impurity into the wafer through the backside surface of the wafer to lower the first resistivity of the portion of the wafer to a second resistivity; after performing the ion implantation process, removing the mask layer from the front-side surface of the wafer; and forming semiconductor devices on the front-side surface of the wafer.
    Type: Grant
    Filed: February 7, 2021
    Date of Patent: June 20, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yao-Wen Hsu, Ching-Hung Kao, Po-Jen Wang, Tsung-Han Tsai
  • Publication number: 20230170603
    Abstract: An electronic device including a substrate, a first metal pattern, a first insulating pattern, and a second metal pattern is provided. The first metal pattern is disposed on the substrate. The first insulating pattern is disposed on the first metal pattern. The second metal pattern is disposed on the first metal pattern and the first insulating pattern. The second metal pattern includes a first contact portion and a second contact portion. In a cross-sectional view, the first contact portion and the second contact portion are in contact with the first metal pattern, and the first insulating pattern is in contact with the first metal pattern and the second metal pattern between the first contact portion and the second contact portion.
    Type: Application
    Filed: October 27, 2022
    Publication date: June 1, 2023
    Applicant: Innolux Corporation
    Inventors: Chung-Chun Cheng, Chia-Chi Ho, Chia-Ping Tseng, Yan-Zheng Wu, Yao-Wen Hsu
  • Publication number: 20230119959
    Abstract: An electronic component includes: an insulating layer; and a first metal bump disposed on the insulating layer and provided with: a first metal layer disposed on the insulating layer; and a second metal layer disposed on the first metal layer, wherein, in a cross-sectional view of the electronic component, the first metal layer has a first width, the second metal layer has a second width, and the first width is smaller than the second width.
    Type: Application
    Filed: November 24, 2021
    Publication date: April 20, 2023
    Inventors: Chung-Chun CHENG, Kuang-Ming FAN, Yao-Wen HSU
  • Publication number: 20230039596
    Abstract: A method for making a semiconductor structure includes forming a first fin and a second fin over a substrate. The method includes forming one or more work function layers over the first and second fins. The method includes forming a nitride-based metal film over the one or more work function layers. The method includes covering the first fin with a patternable layer. The method includes removing a second portion of the nitride-based metal film from the second fin, while leaving a first portion of the nitride-based metal film over the first fin substantially intact.
    Type: Application
    Filed: August 5, 2021
    Publication date: February 9, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yao-Wen Hsu, Ying-Liang Chuang
  • Publication number: 20220319933
    Abstract: Semiconductor devices and methods which utilize a treatment process of a bottom anti-reflective layer are provided. The treatment process may be a physical treatment process in which material is added in order to fill holes and pores within the material of the bottom anti-reflective layer or else the treatment process may be a chemical treatment process in which a chemical reaction is used to form a protective layer. By treating the bottom anti-reflective layer the diffusion of subsequently applied chemicals is reduced or eliminated, thereby helping to prevent defects that arise from such diffusion.
    Type: Application
    Filed: June 13, 2022
    Publication date: October 6, 2022
    Inventors: Yao-Wen Hsu, Ming-Chi Huang, Ying-Liang Chuang
  • Publication number: 20220277989
    Abstract: An opening is formed within a dielectric material overlying a semiconductor substrate. The opening may comprise a via portion and a trench portion. During the manufacturing process a treatment chemical is placed into contact with the exposed surfaces in order to release charges that have built up on the surfaces. By releasing the charges, a surface change potential difference is reduced, helping to prevent galvanic corrosion from occurring during further manufacturing.
    Type: Application
    Filed: May 16, 2022
    Publication date: September 1, 2022
    Inventors: Yao-Wen Hsu, Ming-Che Ku, Neng-Jye Yang, Yu-Wen Wang
  • Patent number: 11362006
    Abstract: Semiconductor devices and methods which utilize a treatment process of a bottom anti-reflective layer are provided. The treatment process may be a physical treatment process in which material is added in order to fill holes and pores within the material of the bottom anti-reflective layer or else the treatment process may be a chemical treatment process in which a chemical reaction is used to form a protective layer. By treating the bottom anti-reflective layer the diffusion of subsequently applied chemicals is reduced or eliminated, thereby helping to prevent defects that arise from such diffusion.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: June 14, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yao-Wen Hsu, Ming-Chi Huang, Ying-Liang Chuang
  • Patent number: 11335589
    Abstract: An opening is formed within a dielectric material overlying a semiconductor substrate. The opening may comprise a via portion and a trench portion. During the manufacturing process a treatment chemical is placed into contact with the exposed surfaces in order to release charges that have built up on the surfaces. By releasing the charges, a surface change potential difference is reduced, helping to prevent galvanic corrosion from occurring during further manufacturing.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: May 17, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yao-Wen Hsu, Ming-Che Ku, Neng-Jye Yang, Yu-Wen Wang
  • Publication number: 20210366704
    Abstract: A semiconductor device and method of manufacture are provided. After a patterning of a middle layer, the middle layer is removed. In order to reduce or prevent damage to other underlying layers exposed by the patterning of the middle layer and intervening layers, an inhibitor is included within an etching process in order to inhibit the amount of material removed from the underlying layers.
    Type: Application
    Filed: August 2, 2021
    Publication date: November 25, 2021
    Inventors: Jian-Jou Lian, Yao-Wen Hsu, Neng-Jye Yang, Li-Min Chen, Chia-Wei Wu, Kuan-Lin Chen, Kuo Bin Huang
  • Patent number: 11081350
    Abstract: A semiconductor device and method of manufacture are provided. After a patterning of a middle layer, the middle layer is removed. In order to reduce or prevent damage to other underlying layers exposed by the patterning of the middle layer and intervening layers, an inhibitor is included within an etching process in order to inhibit the amount of material removed from the underlying layers.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: August 3, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jian-Jou Lian, Yao-Wen Hsu, Neng-Jye Yang, Li-Min Chen, Chia-Wei Wu, Kuan-Lin Chen, Kuo Bin Huang
  • Publication number: 20210159066
    Abstract: A method comprises depositing a mask layer on a front-side surface of a wafer, wherein a portion of the wafer has a first resistivity; with the mask layer in place, performing an ion implantation process on a backside surface of the wafer to implant a resistivity reduction impurity into the wafer through the backside surface of the wafer to lower the first resistivity of the portion of the wafer to a second resistivity; after performing the ion implantation process, removing the mask layer from the front-side surface of the wafer; and forming semiconductor devices on the front-side surface of the wafer.
    Type: Application
    Filed: February 7, 2021
    Publication date: May 27, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yao-Wen HSU, Ching-Hung KAO, Po-Jen WANG, Tsung-Han TSAI
  • Publication number: 20210125877
    Abstract: Semiconductor devices and methods which utilize a treatment process of a bottom anti-reflective layer are provided. The treatment process may be a physical treatment process in which material is added in order to fill holes and pores within the material of the bottom anti-reflective layer or else the treatment process may be a chemical treatment process in which a chemical reaction is used to form a protective layer. By treating the bottom anti-reflective layer the diffusion of subsequently applied chemicals is reduced or eliminated, thereby helping to prevent defects that arise from such diffusion.
    Type: Application
    Filed: June 1, 2020
    Publication date: April 29, 2021
    Inventors: Yao-Wen Hsu, Ming-Chi Huang, Ying-Liang Chuang
  • Patent number: 10916416
    Abstract: A semiconductor wafer and a semiconductor wafer fabrication method are provided. The wafer includes a supporting substrate, a semiconductor substrate and a contact layer. The supporting substrate has a first surface and a second surface opposite to the first surface. The semiconductor substrate is disposed on the first surface of the supporting substrate, in which the semiconductor substrate is configured to form plural devices. The contact layer is disposed on the second surface of the supporting substrate to contact the supporting substrate, in which the contact layer is configured to contact an electrostatic chuck and has a resistivity of the contact layer smaller than a resistivity of the supporting substrate. In semiconductor wafer fabrication method, at first, a raw wafer is provided. Then, the contact layer is formed by using an implantation operation or a deposition operation.
    Type: Grant
    Filed: October 26, 2018
    Date of Patent: February 9, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yao-Wen Hsu, Ching-Hung Kao, Po-Jen Wang, Tsung-Han Tsai
  • Patent number: 10867803
    Abstract: A method of manufacturing a semiconductor device includes exposing a material to a semi-aqueous etching solution. The semi-aqueous etching solution comprises a solvent which chelates with the material and acts as a catalyst between the etching driving force and the material. As such, the etching driving force may be used to remove the material.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yao-Wen Hsu, Jian-Jou Lian, Neng-Jye Yang, Chia-Wei Wu, Kuan-Lin Chen, Kuo Bin Huang, Li-Min Chen
  • Publication number: 20200312711
    Abstract: An opening is formed within a dielectric material overlying a semiconductor substrate. The opening may comprise a via portion and a trench portion. During the manufacturing process a treatment chemical is placed into contact with the exposed surfaces in order to release charges that have built up on the surfaces. By releasing the charges, a surface change potential difference is reduced, helping to prevent galvanic corrosion from occurring during further manufacturing.
    Type: Application
    Filed: June 15, 2020
    Publication date: October 1, 2020
    Inventors: Yao-Wen Hsu, Ming-Che Ku, Neng-Jye Yang, Yu-Wen Wang
  • Patent number: 10685870
    Abstract: An opening is formed within a dielectric material overlying a semiconductor substrate. The opening may comprise a via portion and a trench portion. During the manufacturing process a treatment chemical is placed into contact with the exposed surfaces in order to release charges that have built up on the surfaces. By releasing the charges, a surface change potential difference is reduced, helping to prevent galvanic corrosion from occurring during further manufacturing.
    Type: Grant
    Filed: February 15, 2018
    Date of Patent: June 16, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yao-Wen Hsu, Ming-Che Ku, Neng-Jye Yang, Yu-Wen Wang
  • Publication number: 20200083038
    Abstract: A semiconductor device and method of manufacture are provided. After a patterning of a middle layer, the middle layer is removed. In order to reduce or prevent damage to other underlying layers exposed by the patterning of the middle layer and intervening layers, an inhibitor is included within an etching process in order to inhibit the amount of material removed from the underlying layers.
    Type: Application
    Filed: November 18, 2019
    Publication date: March 12, 2020
    Inventors: Jian-Jou Lian, Yao-Wen Hsu, Neng-Jye Yang, Li-Min Chen, Chia-Wei Wu, Kuan-Lin Chen, Kuo Bin Huang