Abstract: Provided are a display panel and a display device. The display panel includes: a pixel unit, including a pixel circuit and a light-emitting element a data line connected with the pixel circuit the data line includes first-type data lines and second-type data lines, the second-type data line includes a first portion, a second portion, and a third portion the third portion is connected with the first portion through a first via hole, the third portion is connected with the second portion through a second via hole, and the third portion includes a main trace located between the first via hole and the second via hole, at least one third portion includes a compensation trace, the compensation trace of the third portion is located at least one end of the main trace of the third portion, lengths of the plurality of third portions are equal or approximately equal.

Abstract: A semiconductor package includes a package substrate, an interposer module on the package substrate, and a package lid on the interposer module and including a vapor chamber base, the vapor chamber base including a plate portion, and an angled portion extending at an angle from opposing ends of the plate portion. A method of cooling the semiconductor package may include locating the semiconductor package in an immersion cooling chamber, immersing the semiconductor package in an immersion coolant in the immersion cooling chamber such that a plate portion and an angled portion of a vapor chamber base of the package lid is immersed in the immersion coolant, and transferring heat from the plate portion and angled portion of the vapor chamber base to the immersion coolant to cool the semiconductor package.

Abstract: An out-of-order buffer includes an out-of-order queue and a controlling circuit. The out-of-order queue includes a request sequence table and a request storage device. The controlling circuit receives and temporarily stores the plural requests into the out-of-order queue. After the plural requests are transmitted to plural corresponding target devices, the controlling circuit retires the plural requests. The request sequence table contains m×n indicating units. The request sequence table contains m entry indicating rows. Each of the m entry indicating rows contains n indicating units. The request storage device includes m storage units corresponding to the m entry indicating rows in the request sequence table. The state of indicating whether one request is stored in the corresponding storage unit of the m storage units is recoded in the request sequence table. The storage sequence of the plural requests is recoded in the request sequence table.

Abstract: A display panel has a first region and a second region. The display panel includes: a plurality of first light-emitting devices in the first region; a plurality of second light-emitting devices, a plurality of first pixel circuits, and a plurality of second pixel circuits in the second region; and a plurality of connection lines in the first region and the second region. At least one first pixel circuit is electrically connected to at least one first light-emitting device through at least one connection line, at least one second pixel circuit is electrically connected to at least one second light-emitting device. The at least one row of first light-emitting devices includes light-emitting repeat units arranged in a first direction, and a light-emitting repeat unit includes first light-emitting devices; and connection lines connected to at least two first light-emitting devices in the light-emitting repeat units are made of different materials.

Abstract: Provided are an anti-PD-1/anti-HER2 natural antibody structural heterodimeric bispecific antibody and a method of preparing the same. More particularly, provided are a highly stable heterodimeric anti-PD-1/anti-HER2 bispecific antibody having natural IgG characteristics without mismatch between a heavy chain and a light chain, and a method of preparing the same. The bispecific antibody may bind to two target molecules simultaneously and has excellent effects in treatment of a complex disease.

Abstract: A pixel scan drive circuit including a switch unit, a pull-up output unit and a pull-down output unit is provided. In a scan signal output phase of a scanning cycle, the pull-down output unit outputs a first reference voltage in a scan signal to an output end according to a clock signal. In a maintenance phase of the scanning cycle, the switch unit controls the voltage of a pull-down node according to a switch control signal, thereby controlling the pull-down output unit to stop outputting the first reference voltage. In the maintenance phase, the pull-up output unit outputs a second reference voltage in the scan signal. The second reference voltage controls the pixel units to stop receiving the image data. Transistors in the switch unit are of different types from transistors in the pull-up output unit and the pull-down output unit. An array substrate and a display terminal are provided.

Abstract: Provided is a light emitting scanning drive unit (EOA), including a pull-up control unit (11), a pull-up output unit (12), a pull-down control unit (14) and a pull-down output unit (13). When receiving a first clock signal (ECKi), the pull-up control unit (11) transmits the high-level reference voltage to the pull-up node (PU) to control the pull-up point (PU) to be in the high-level state, meanwhile, the pull-up output unit (12) transmits the high-level reference voltage to the light emitting scanning terminal (Oe) when it is in the high-level state and outputs the high-level reference voltage as the light emitting scanning signal.

Abstract: The present invention provides a scanning drive circuit (10), including a pull-down control module (100), a pull-down output module (200), a pull-up control module (300) and an output end (Eout), where a first node (PD) is arranged between the pull-down control module (100) and the pull-down output module (200), the pull-down control module (100) and the pull-down output module (200) are respectively electrically connected to the first node (PD), and the output end (Eout) is configured to be connected to a light-emitting unit. Whether in a data write-in stage or a light-emitting stage, the pull-down control module (100) controls a potential of the first node (PD) which controls an input result input to the output end (Eout) from the pull-down output module (200). So, the light-emitting unit can be controlled to emit light in time, thereby improving a light-emitting display effect. The present invention further provides a display panel.

Abstract: The present disclosure provides a light-emitting scanning signal drive circuit, a display panel and an electronic device. The light-emitting scanning signal drive circuit includes: an enable signal generation circuit and a regulation circuit, where the enable signal generation circuit is configured to receive a first voltage signal and includes a pull-up point, a pull-down point and an output terminal, the pull-up point is electrically connected to the regulation circuit, the pull-down point is electrically connected to the regulation circuit, the regulation circuit is configured to receive a second voltage signal and input the second voltage signal to the enable signal generation circuit, and the enable signal generation circuit generates a high-potential enable signal based on the first voltage signal and the second voltage signal and outputs the high-potential enable signal via the output terminal. The leakage current of the enable signal generation circuit is reduced.

Abstract: A pixel scan drive circuit including a switch unit, a pull-up output unit and a pull-down output unit is provided. In a scan signal output phase of a scanning cycle, the pull-down output unit outputs a first reference voltage in a scan signal to an output end according to a clock signal. In a maintenance phase of the scanning cycle, the switch unit controls the voltage of a pull-down node according to a switch control signal, thereby controlling the pull-down output unit to stop outputting the first reference voltage. In the maintenance phase, the pull-up output unit outputs a second reference voltage in the scan signal. The second reference voltage controls the pixel units to stop receiving the image data. Transistors in the switch unit are of different types from transistors in the pull-up output unit and the pull-down output unit. An array substrate and a display terminal are provided.

Abstract: Provided are an anti-PD-1/anti-HER2 natural antibody structural heterodimeric bispecific antibody and a method of preparing the same. More particularly, provided are a highly stable heterodimeric anti-PD-1/anti-HER2 bispecific antibody having natural IgG characteristics without mismatch between a heavy chain and a light chain, and a method of preparing the same. The bispecific antibody may bind to two target molecules simultaneously and has excellent effects in treatment of a complex disease.

Abstract: The array substrate, the liquid crystal display panel and the liquid crystal display device of the present disclosure are designed to form the MIS storage capacitor by the P—Si semiconductor layer, the first metal layer and the insulating layer between above or the P—Si semiconductor layer, the second metal layer and the dielectric spacer layer between above, when one side of the first metal layer or the second metal layer receiving the negative gray voltage, the P—Si in the P—Si semiconductor layer will gather to form the hole, when receiving the positive gray voltage, will form the depletion layer on the upper layer of the P—Si to reduce the capacity of the MIS storage capacitor, thereby reducing the difference of the capacitance when the MIS storage capacitor in the positive and negative gray voltage, improving the flicker phenomena and ensuring the display effect.

Abstract: The array substrate, the liquid crystal display panel and the liquid crystal display device of the present disclosure are designed to form the MIS storage capacitor by the P—Si semiconductor layer, the first metal layer and the insulating layer between above or the P—Si semiconductor layer, the second metal layer and the dielectric spacer layer between above, when one side of the first metal layer or the second metal layer receiving the negative gray voltage, the P—Si in the P—Si semiconductor layer will gather to form the hole, when receiving the positive gray voltage, will form the depletion layer on the upper layer of the P—Si to reduce the capacity of the MIS storage capacitor, thereby reducing the difference of the capacitance when the MIS storage capacitor in the positive and negative gray voltage, improving the flicker phenomena and ensuring the display effect.

Abstract: The array substrate, the liquid crystal display panel and the liquid crystal display device of the present disclosure are designed to from the MIS storage capacitor by the P-Si semiconductor layer, the first metal layer and the insulating layer between above or the P-Si semiconductor layer, the second metal layer and the dielectric spacer layer between above, when one side of the first metal layer or the second metal layer receiving the negative gray voltage, the P-Si in the P-Si semiconductor layer will gather to form the hole, when receiving the positive gray voltage, will form the depletion layer on the upper layer of the P-Si to reduce the capacity of the MIS storage capacitor, thereby reducing the difference of the capacitance when the MIS storage capacitor in the positive and negative gray voltage, improving the flicker phenomena and ensuring the display effect.

Abstract: A GOA circuit, a display device, and a driving method of GOA circuit are disclosed. A N-th level GOA unit is configured for charging the N-th level horizontal scanning line (G(N)) within a display area of the display device. The N-th level horizontal scanning line (G(N)) connects to GAS. In response to the GAS, the horizontal scanning lines corresponding to all of the GOA units are in a charging state. In this way, the horizontal scanning lines at each level are connected to the GAS, such that when the GAS are valid, the corresponding horizontal scanning line at each level are in the charging state of in an on-state so as to realize the All Gate On function.

Abstract: The array substrate, the liquid crystal display panel and the liquid crystal display device of the present disclosure are designed to form the MIS storage capacitor by the P—Si semiconductor layer, the first metal layer and the insulating layer between above or the P—Si semiconductor layer, the second metal layer and the dielectric spacer layer between above, when one side of the first metal layer or the second metal layer receiving the negative gray voltage, the P—Si in the P—Si semiconductor layer will gather to form the hole, when receiving the positive gray voltage, will form the depletion layer on the upper layer of the P—Si to reduce the capacity of the MIS storage capacitor, thereby reducing the difference of the capacitance when the MIS storage capacitor in the positive and negative gray voltage, improving the flicker phenomena and ensuring the display effect.

Abstract: The array substrate, the liquid crystal display panel and the liquid crystal display device of the present disclosure are designed to form the MIS storage capacitor by the P—Si semiconductor layer, the first metal layer and the insulating layer between above or the P—Si semiconductor layer, the second metal layer and the dielectric spacer layer between above, when one side of the first metal layer or the second metal layer receiving the negative gray voltage, the P—Si in the P—Si semiconductor layer will gather to form the hole, when receiving the positive gray voltage, will form the depletion layer on the upper layer of the P—Si to reduce the capacity of the MIS storage capacitor, thereby reducing the difference of the capacitance when the MIS storage capacitor in the positive and negative gray voltage, improving the flicker phenomena and ensuring the display effect.

Abstract: The array substrate, the liquid crystal display panel and the liquid crystal display device of the present disclosure are designed to from the MIS storage capacitor by the P-Si semiconductor layer, the first metal layer and the insulating layer between above or the P-Si semiconductor layer, the second metal layer and the dielectric spacer layer between above, when one side of the first metal layer or the second metal layer receiving the negative gray voltage, the P-Si in the P-Si semiconductor layer will gather to form the hole, when receiving the positive gray voltage, will form the depletion layer on the upper layer of the P-Si to reduce the capacity of the MIS storage capacitor, thereby reducing the difference of the capacitance when the MIS storage capacitor in the positive and negative gray voltage, improving the flicker phenomena and ensuring the display effect.

Abstract: A gate on array (GOA) circuit for used in an LCD includes GOA units connected in cascade. An Nth GOA unit includes an Nth stage-transmittance circuit, an Nth Q-node controlling circuit, an Nth P-node controlling circuit, an Nth outputting circuit, and a first switch circuit where N is a positive integer. The first switch circuit connected to the Nth scanning line, for inputting an enabling signal to the Nth scanning line before the LCD shows images so as to turn on a TFT in a pixel which the Nth scanning line is connected to. The benefit of the function is that the display does not leak electricity when the black screen is woken up and that the stability of the circuit is enhanced at the same time.

Abstract: The array substrate, the liquid crystal display panel and the liquid crystal display device of the present disclosure are designed to from the MIS storage capacitor by the P—Si semiconductor layer, the first metal layer and the insulating layer between above or the P—Si semiconductor layer, the second metal layer and the dielectric spacer layer between above, when one side of the first metal layer or the second metal layer receiving the negative gray voltage, the P—Si in the P—Si semiconductor layer will gather to form the hole, when receiving the positive gray voltage, will form the depletion layer on the upper layer of the P—Si to reduce the capacity of the MIS storage capacitor, thereby reducing the difference of the capacitance when the MIS storage capacitor in the positive and negative gray voltage, improving the flicker phenomena and ensuring the display effect.