Patents by Inventor Yao YANG

Yao YANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180226669
    Abstract: The disclosure relates to a method for using fuel cell. The fuel cell includes a container, wherein the container comprises a housing and a nozzle, and the housing defines through holes; the housing defines a chamber and an opening; the nozzle has a first end in air/fluid communication with the opening and a second end; and a membrane electrode assembly, which is flexible, on the container to form a curved membrane electrode assembly surrounding the chamber and covering the through holes, wherein the membrane electrode assembly comprises a proton exchange membrane having a first surface and a second surface, a cathode electrode on the first surface and an anode electrode on the second surface. The method includes at least partially immersing the fuel cell in a fuel; and supplying an oxidizing gas into the chamber.
    Type: Application
    Filed: April 9, 2018
    Publication date: August 9, 2018
    Inventors: LI-NA ZHANG, XIN-YU GAO, QI-YAO YANG, KAI-LI JIANG, CHANG-HONG LIU, SHOU-SHAN FAN
  • Publication number: 20180158943
    Abstract: A semiconductor device includes a semiconductor substrate, a gate structure formed over the semiconductor substrate, and an epitaxial structure formed partially within the semiconductor substrate. The gate structure includes a gate dielectric layer formed over the semiconductor substrate, a gate electrode formed over the gate dielectric layer, and a spacer formed on side surfaces of the gate dielectric layer and the gate electrode. A laterally extending portion of the epitaxial structure extends laterally at an area below a top surface of the semiconductor substrate in a direction toward an area below the gate structure. A lateral end of the laterally extending portion is below the spacer.
    Type: Application
    Filed: February 6, 2018
    Publication date: June 7, 2018
    Inventors: Yu-Ying Lin, Kuan Hsuan KU, I-Cheng Hu, Chueh-Yang Liu, Shui-Yen Lu, Yu Shu LIN, Chun Yao YANG, Yu-Ren Wang, Neng-Hui Yang
  • Publication number: 20180138853
    Abstract: An electronically commutated fan system includes an alternating-current-to-direct-current conversion unit, an inverter unit and a control unit. The alternating-current-to-direct-current conversion unit converts an alternating-current input power source into a first direct-current power source. The inverter unit is electrically connected between the alternating-current-to-direct-current conversion unit and a fan. The inverter unit converts the first direct-current power source into an alternating-current output power source and provides the alternating-current output power source to the fan to rotate. The control unit is electrically connected to the alternating-current-to-direct-current conversion unit and the inverter unit. The control unit controls the alternating-current-to-direct-current conversion unit and the inverter unit to adjust a rotational speed of the fan.
    Type: Application
    Filed: December 6, 2016
    Publication date: May 17, 2018
    Inventors: Wei-Shuo TSENG, Chao-Chin CHUANG, Yao-Yang YU, Li-Wei HSIAO
  • Patent number: 9966434
    Abstract: A semiconductor device includes a substrate including a plurality of transistor devices formed thereon, at least an epitaxial structure formed in between the transistor devices, and a tri-layered structure formed on the epitaxial structure. The epitaxial structure includes a first semiconductor material and a second semiconductor material, and a lattice constant of the second semiconductor material is larger than a lattice constant of the first semiconductor material. The tri-layered structure includes an undoped epitaxial layer, a metal-semiconductor compound layer, and a doped epitaxial layer sandwiched in between the undoped epitaxial layer and the metal-semiconductor compound layer. The undoped epitaxial layer and the doped epitaxial layer include at least the second semiconductor material.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: May 8, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ming-Shiou Hsieh, Chun-Yao Yang, Shi-You Liu, Rong-Sin Lin, Han-Ting Yen, Yi-Wei Chen, I-Cheng Hu, Yu-Shu Lin, Neng-Hui Yang
  • Patent number: 9952939
    Abstract: In some embodiments of the present invention, a data storage system includes a controller and a non-volatile memory array having a plurality of memory pages. The controller performs a method that efficiently resolves the lower page corruption problem. In one embodiment, the method selects programmed lower page(s) for which paired upper page(s) have not been programmed, reads data from those selected lower page(s), corrects the read data, and reprograms the read data into those lower page(s). Since the number of lower pages in this condition is typically low (e.g., several pages in a block with hundreds or thousands of pages), this is a much more efficient method than reprogramming the entire block. In another embodiment, a similar reprogramming method is applied as a data recovery scheme in situations in which only lower pages are programmed (e.g., SLC memory, MLC memory in SLC mode, etc.).
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: April 24, 2018
    Assignee: Western Digital Technologies, Inc.
    Inventors: Yongke Sun, Dengtao Zhao, Jui-Yao Yang
  • Publication number: 20180108570
    Abstract: A method for manufacturing fins includes following steps. A substrate including a plurality of fins formed thereon is provided. At least an ion implantation is performed to the fins. A thermal process is performed after the ion implantation. An insulating layer is formed on the substrate, and the fins are embedded in the insulating layer. Thereafter, a portion of the insulating layer is removed to form an isolation structure on the substrate, and the fins are exposed from a top surface of the isolation structure. The insulating layer is formed after the ion implantation and the thermal process. Or, the isolation structure is formed before the ion implantation, or between the ion implantation and the thermal process.
    Type: Application
    Filed: November 19, 2017
    Publication date: April 19, 2018
    Inventors: Ming-Shiou Hsieh, Chun-Yao Yang, Shi-You Liu, Rong-Sin Lin, Han-Ting Yen, Neng-Hui Yang, Tsai-Yu Wen, Ching-I Li
  • Patent number: 9947588
    Abstract: A method for manufacturing fins includes following steps. A substrate including a plurality of fins formed thereon is provided. At least an ion implantation is performed to the fins. A thermal process is performed after the ion implantation. An insulating layer is formed on the substrate, and the fins are embedded in the insulating layer. Thereafter, a portion of the insulating layer is removed to form an isolation structure on the substrate, and the fins are exposed from a top surface of the isolation structure. The insulating layer is formed after the ion implantation and the thermal process. Or, the isolation structure is formed before the ion implantation, or between the ion implantation and the thermal process.
    Type: Grant
    Filed: November 19, 2017
    Date of Patent: April 17, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ming-Shiou Hsieh, Chun-Yao Yang, Shi-You Liu, Rong-Sin Lin, Han-Ting Yen, Neng-Hui Yang, Tsai-Yu Wen, Ching-I Li
  • Patent number: 9935322
    Abstract: The disclosure relates to a fuel cell system. The fuel cell system includes a fuel cell module, fuel and oxidizing gas. The fuel cell module includes a container and a membrane electrode assembly located on the container. The container includes a housing and a nozzle connected to the housing. The container defines a number of through holes located on the housing and covered by the membrane electrode assembly. The membrane electrode assembly includes a proton exchange membrane having a first surface and a second surface opposite to the first surface, a cathode electrode located on the first surface and an anode electrode located on the second surface.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: April 3, 2018
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Li-Na Zhang, Xin-Yu Gao, Qi-Yao Yang, Kai-Li Jiang, Chang-Hong Liu, Shou-Shan Fan
  • Patent number: 9929423
    Abstract: The disclosure relates to a fuel cell module. The fuel cell module includes a container and a membrane electrode assembly located on the container. The container includes a housing and a nozzle connected to the housing. The container defines a number of through holes located on the housing and covered by the membrane electrode assembly. The membrane electrode assembly includes a proton exchange membrane having a first surface and a second surface opposite to the first surface, a cathode electrode located on the first surface and an anode electrode located on the second surface.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: March 27, 2018
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Li-Na Zhang, Xin-Yu Gao, Qi-Yao Yang, Kai-Li Jiang, Chang-Hong Liu, Shou-Shan Fan
  • Patent number: 9929264
    Abstract: A semiconductor device includes a semiconductor substrate, a gate structure formed over the semiconductor substrate, and an epitaxial structure formed partially within the semiconductor substrate. A vertically extending portion of the epitaxial structure extends vertically above a top surface of the semiconductor substrate in an area adjacent the gate structure. A laterally extending portion of the epitaxial structure extends laterally at an area below the top surface of the semiconductor substrate in a direction toward an area below the gate structure and beyond an area where the epitaxial structure extends vertically. The device further includes an interlayer dielectric layer between a side surface of the vertically extending portion of the epitaxial structure and a side surface of the gate structure. A top surface of the laterally extending portion of the epitaxial structure directly contacts the interlayer dielectric layer.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: March 27, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Ying Lin, Kuan Hsuan Ku, I-Cheng Hu, Chueh-Yang Liu, Shui-Yen Lu, Yu Shu Lin, Chun Yao Yang, Yu-Ren Wang, Neng-Hui Yang
  • Patent number: 9859164
    Abstract: A method for manufacturing fins includes following steps. A substrate including a plurality of fins formed thereon is provided. At least an ion implantation is performed to the fins. A thermal process is performed after the ion implantation. An insulating layer is formed on the substrate, and the fins are embedded in the insulating layer. Thereafter, a portion of the insulating layer is removed to form an isolation structure on the substrate, and the fins are exposed from a top surface of the isolation structure. The insulating layer is formed after the ion implantation and the thermal process. Or, the isolation structure is formed before the ion implantation, or between the ion implantation and the thermal process.
    Type: Grant
    Filed: October 17, 2016
    Date of Patent: January 2, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ming-Shiou Hsieh, Chun-Yao Yang, Shi-You Liu, Rong-Sin Lin, Han-Ting Yen, Neng-Hui Yang, Tsai-Yu Wen, Ching-I Li
  • Publication number: 20170365703
    Abstract: A semiconductor device includes a semiconductor substrate, a gate structure formed over the semiconductor substrate, and an epitaxial structure formed partially within the semiconductor substrate. A vertically extending portion of the epitaxial structure extends vertically above a top surface of the semiconductor substrate in an area adjacent the gate structure. A laterally extending portion of the epitaxial structure extends laterally at an area below the top surface of the semiconductor substrate in a direction toward an area below the gate structure and beyond an area where the epitaxial structure extends vertically. The device further includes an interlayer dielectric layer between a side surface of the vertically extending portion of the epitaxial structure and a side surface of the gate structure. A top surface of the laterally extending portion of the epitaxial structure directly contacts the interlayer dielectric layer.
    Type: Application
    Filed: June 20, 2017
    Publication date: December 21, 2017
    Inventors: Yu-Ying LIN, Kuan Hsuan KU, I-Cheng HU, Chueh-Yang LIU, Shui-Yen LU, Yu Shu LIN, Chun Yao YANG, Yu-Ren WANG, Neng-Hui YANG
  • Patent number: 9842760
    Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate having a fin-shaped structure thereon is provided, a spacer is formed adjacent to the fin-shaped structure, and the spacer is used as mask to remove part of the substrate for forming an isolation trench, in which the isolation trench includes two sidewall portions and a bottom portion. Next, a plasma doping process is conducted to implant dopants into the two sidewall portions and the bottom portion of the isolation trench.
    Type: Grant
    Filed: July 20, 2016
    Date of Patent: December 12, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Li-Wei Feng, Tong-Jyun Huang, Shih-Hung Tsai, Jyh-Shyang Jenq, Chun-Yao Yang, Ming-Shiou Hsieh, Rong-Sin Lin
  • Publication number: 20170352423
    Abstract: Systems and methods for managing data retention in a solid-state storage system utilizing data retention flag bytes are disclosed. A data storage device includes a non-volatile memory comprising a plurality of non-volatile memory devices and a controller configured to write data to a memory unit of the non-volatile memory array and write a data retention flag value indicating a number of bits of the written data programmed in a first of a plurality of logical states. The controller is further configured to read the data and determine a number of bits having the first of the plurality of logical states in the read data, and determine a difference between the number of bits of the written data programmed in the first logical state and the number of bits having the first logical state in the read data. The difference is used to determine data retention characteristics of the non-volatile memory.
    Type: Application
    Filed: April 10, 2017
    Publication date: December 7, 2017
    Inventors: Dengtao Zhao, Yongke Sun, Haibo Li, Jui-Yao Yang, Kroum Stoev
  • Publication number: 20170330937
    Abstract: A semiconductor device includes a substrate including a plurality of transistor devices formed thereon, at least an epitaxial structure formed in between the transistor devices, and a tri-layered structure formed on the epitaxial structure. The epitaxial structure includes a first semiconductor material and a second semiconductor material, and a lattice constant of the second semiconductor material is larger than a lattice constant of the first semiconductor material. The tri-layered structure includes an undoped epitaxial layer, a metal-semiconductor compound layer, and a doped epitaxial layer sandwiched in between the undoped epitaxial layer and the metal-semiconductor compound layer. The undoped epitaxial layer and the doped epitaxial layer include at least the second semiconductor material.
    Type: Application
    Filed: June 26, 2017
    Publication date: November 16, 2017
    Inventors: Ming-Shiou Hsieh, Chun-Yao Yang, Shi-You Liu, Rong-Sin Lin, Han-Ting Yen, Yi-Wei Chen, I-Cheng Hu, Yu-Shu Lin, Neng-Hui Yang
  • Patent number: 9763651
    Abstract: A tendon stripper includes a stripping device and a rod. The stripping device includes a stripping member and at least one coupling member coupling to the stripping member. The stripping member has a blade portion and a separating portion separating the stripping member into several parts. The rod has a handle end and a coupling end opposite to the handle end. The coupling end couples to the coupling member of the stripping device. The separating portion allows the stripping member to be divided into first and second parts, and the first and second parts can be combined to each other to jointly receive the tendon. This avoids the generation of the incisions during the tendon transplantation. In addition, since the tendon stripper does not require any instrument for retaining the free end of the tendon, a convenient surgical procedure is provided.
    Type: Grant
    Filed: April 15, 2015
    Date of Patent: September 19, 2017
    Assignee: E-Da Hospital
    Inventors: Chih-Kun Hsiao, Yuan-Kun Tu, Teng-Yao Yang, Feng-Chen Kao, Yi-Jung Tsai, Hao-Yuan Hsiao
  • Patent number: 9757064
    Abstract: A wrist joint performance measuring device includes a base having a seat and two positioning arms on two sides of the seat. A switching device is pivotably mounted to the base. A forearm support is connected to the switching device. A measurement device includes a pivotal seat, a torque meter, a first handle, and a second handle. The pivotal seat is pivotably connected to the forearm support. The torque meter is mounted to the pivotal seat. The first handle or the second handle is connected to a force receiving end of the torque meter. The forearm support and the measurement device are movable by the switching device to one of the two positioning arms and are positioned by the one of the two positioning arms.
    Type: Grant
    Filed: July 1, 2015
    Date of Patent: September 12, 2017
    Assignee: E-Da Hospital
    Inventors: Chih-Kun Hsiao, Yuan-Kun Tu, Yi-Jung Tsai, Teng-Yao Yang, Shang-Hua Yu, Chun-Wei Kang, Hao-Yuan Hsiao
  • Patent number: 9747680
    Abstract: A method for vision machine inspection comprises providing depth information of a target acquired by an image capturing system, determining real-time three-dimensional information of a target object in a predetermined inspecting area based on depth information of at least one real-time image of the target. The method further comprises projecting color pixel information of a real-time color image of the target object to a three-dimensional virtual model based on the real-time three-dimensional information. The real-time color image may be acquired by a color camera system. The method further comprises generating a color three-dimensional virtual model. The color three-dimensional virtual model may comprise the color pixel information.
    Type: Grant
    Filed: November 27, 2013
    Date of Patent: August 29, 2017
    Assignee: Industrial Technology Research Institute
    Inventors: Chung-Li Tai, Chih-Kai Chiu, Yao-Yang Tsai
  • Patent number: 9722030
    Abstract: A semiconductor device includes a substrate including a plurality of transistor devices formed thereon, at least an epitaxial structure formed in between the transistor devices, and a tri-layered structure formed on the epitaxial structure. The epitaxial structure includes a first semiconductor material and a second semiconductor material, and a lattice constant of the second semiconductor material is larger than a lattice constant of the first semiconductor material. The tri-layered structure includes an undoped epitaxial layer, a metal-semiconductor compound layer, and a doped epitaxial layer sandwiched in between the undoped epitaxial layer and the metal-semiconductor compound layer. The undoped epitaxial layer and the doped epitaxial layer include at least the second semiconductor material.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: August 1, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ming-Shiou Hsieh, Chun-Yao Yang, Shi-You Liu, Rong-Sin Lin, Han-Ting Yen, Yi-Wei Chen, I-Cheng Hu, Yu-Shu Lin, Neng-Hui Yang
  • Publication number: 20170212575
    Abstract: A power budget allocation method includes: obtaining a system setting associated with a multi-core processor system, obtaining a target power budget, and checking, by a power management controller, at least one power management table according to the system setting and the target power budget to generate a power management output for the multi-core processor system. The system setting includes a core combination setting of the multi-core processor system, and further includes a frequency setting of each processor core selected by the core combination setting.
    Type: Application
    Filed: January 10, 2017
    Publication date: July 27, 2017
    Inventors: Wei-Ting Wang, Han-Lin Li, Yingshiuan Pan, Yueh-Feng Lee, Shun-Yao Yang, Jih-Ming Hsu