Abstract: A resin composition having lower dielectric constant Dk, lower dielectric loss Df, lower water absorption, higher surface impedance, and higher glass transition temperature includes resins. The resins have a chemical structure selected from a group consisting of or any combination thereof.

Abstract: Within a method for forming a dual damascene aperture there is surface treated a first dielectric layer to form a surface treated first dielectric layer having a first surface composition different than a first bulk composition. There is then formed upon the surface treated first dielectric layer a second dielectric layer having a second bulk composition. Finally, there is then formed through the second dielectric layer a trench contiguous with and overlapping a via formed through the surface treated first dielectric layer. Within the present invention, when forming the trench through the second dielectric layer an endpoint is determined by detecting a difference between the second bulk composition and the first surface composition.

Abstract: A method of coating a low dielectric constant material layer wherein the wafer surface is pre-wetted using a solvent to prevent or reduce coating defects is described. A semiconductor substrate is provided wherein a top surface of the semiconductor substrate may have surface defects. A solvent is coated overlying the top surface of the semiconductor substrate. A low dielectric constant material layer is coated overlying the solvent wherein the solvent covers the surface defects thereby preventing defects in the low dielectric constant material layer.

Abstract: Within a method for forming a dual damascene aperture there is surface treated a first dielectric layer to form a surface treated first dielectric layer having a first surface composition different than a first bulk composition. There is then formed upon the surface treated first dielectric layer a second dielectric layer having a second bulk composition. Finally, there is then formed through the second dielectric layer a trench contiguous with and overlapping a via formed through the surface treated first dielectric layer. Within the present invention, when forming the trench through the second dielectric layer an endpoint is determined by detecting a difference between the second bulk composition and the first surface composition.

Abstract: The present invention provides a method improving the adhesion between inter metal dielectric (IMD) layers by performing a HF dip etch to treat the surface of an oxide, silicon nitride or Silicon oxynitride insulating layer before an overlying low-K layer is formed. The present invention provides a method of fabricating a low-K IMD layer 20 over an oxide, Silicon oxynitride (SiON), or nitride IMD layer 14 with improved adhesion. First, a 1st inter metal dielectric (IMD) layer 14 is formed over a substrate. Next, the invention's novel HF dip etch is performed on the 1st IMD layer 14 to form a treated surface 16. Next, a 2nd BMD layer composed of a low-K material is formed over the rough surface 16 of the 1st IMD layer 14. The treated surface 16 improves the adhesion between a 1st IMD layer oxide (oxide, SiN or SiON) and a low k layer. Subsequent photoresist strip steps do not cause the 1st IMI layer 14 and the 2nd IMD layer 20 (low-K dielectric) to peel.

Abstract: A method for improving the adhesion, between an overlying insulator layer, and an underlying low K layer, used for forming a composite layer, damascene mask pattern, wherein the damascene mask pattern is used as an interlevel dielectric layer, between metal interconnect structures, has been developed. A treatment, comprised of aqueous NH4OH solutions, or of UV curing procedures, is performed on the top surface of the low K layer, prior to deposition of the overlying insulator layer. The treatment, resulting in a roughened top surface of the low K layer, allows removal of masking photoresist shapes, to be aggressively accomplished using wet strippers, without adhesion loss at the insulator—low K layer interface.

Abstract: A method for forming a dielectric layer upon a substrate within a microelectronics fabrication. There is provided a substrate. There is then formed upon the substrate while employing a low dielectric constant spin-on material a dielectric layer which is subsequently cured at atmospheric pressure at an elevated temperature to stabilize the physical and chemical properties of the low dielectric constant dielectric layer so as to attenuate shrinkage and other changes in those physical, and chemical properties from thermal annealing at sub-atmospheric pressure due to typical further microelectronics fabrication processing steps.

Abstract: A process of forming a thin, protective insulator layer, on the sides of metal interconnect structures, prior to the deposition of a halogen containing, low k dielectric layer, has been developed. The process features the growth of a thin metal nitride, or thin metal oxide layer, on the exposed sides of the metal interconnect structures, via a plasma treatment, performed in either a nitrogen containing, or in a water containing, ambient. The thin layer protects the metal interconnect structure from the corrosive, as well as delamination effects, created by the halogen, or halogen products, contained in overlying low k dielectric layers, such as fluorinated silica glass.

Abstract: A process for fabricating a copper damascene structure, embedded in two levels of low dielectric constant, composite insulator layers, has been developed. The process features the use of two levels of low dielectric constant, composite insulator layers, each comprised of an overlying fluorinated silicon glass, (FSG), layer, and an underlying, applied hydrogen silsesquioxane, (HSQ), layer, with a thin silicon oxynitride layer located between levels of the low dielectric constant, composite insulator layers. A wide diameter opening, of a subsequent dual damascene opening, is formed via dry etching procedures, performed in the upper level, composite insulator layer, with the dry etching procedure, selectively terminating at the appearance of the silicon oxynitride layer. The narrow diameter opening, of the dual damascene opening, is next formed in the silicon oxynitride layer, and in the lower level, composite insulator layer, via dry etching procedures.

Abstract: A method for fabricating a hybrid low dielectric constant intermetal dielectric layer with improved reliability for multilevel electrical interconnections on integrated circuits is achieved. After forming metal lines for interconnecting the semiconductor devices, a protective insulating layer composed of a low-k fluorine-doped oxide (k=3.5) is deposited. A porous low-k spin-on dielectric layer (k less than 3) is formed in the gaps between the metal lines to further minimize the intralevel capacitance. A more dense low-k dielectric layer, such as FSG, is deposited on the porous layer to provide improved structural mechanical strength and over the metal lines to provide reduced intralevel capacitance. Via holes are etched in the FSG and are filled with metal plugs and the method can be repeated for additional metal levels to complete the multilevel interconnections on the integrated circuit.

Abstract: A method for forming upon a substrate employed within a microelectronics fabrication a composite dielectric layer with enhanced adhesion. There is first provided a substrate. There is then formed over and upon the substrate a first dielectric layer comprising a silicon, oxygen and nitrogen containing dielectric material in contact with a second dielectric layer comprising an organic polymer spin-on-polymer (SOP) dielectric material. The interface between the dielectric layers may be treated by ion implantation methods to provide the resulting silicon, oxygen and nitrogen containing dielectric layer composition to provide the composite dielectric layer with enhanced adhesion at the interface.

Abstract: A method of forming dielectric films is described wherein the low dielectric constant of a layer of dielectric material having a low dielectric constant, such as low dielectric constant spin-on-glass, is stabilized to prevent subsequent processing steps from increasing the dielectric constant. The layer of dielectric material having a low dielectric constant is treated in an inert atmosphere, such as nitrogen or argon, at an elevated temperature. This inert atmosphere treatment of the dielectric prevents the dielectric constant from increasing during subsequent processing steps.

Abstract: The present invention provides a method of fabricating passivation layers over closely spaced metal lines on a substrate. More particularly, the invention forms a three layer sandwich of passivation layers comprised of (1) a first thin plasma enhance silicon nitride (PE-SiN) layer; (2) a silicon oxide layer; and (3) a second silicon nitride layer. The method begins by forming closely spaced metal lines 20 over a substrate surface. A first silicon nitride layer 24 is formed using a low powered plasma enhanced chemical vapor deposition process, over the metal lines 20 and the substrate surface. A silicon oxide layer 28 is then formed over the first silicon nitride layer. A second nitride layer 32 is formed, using a plasma enhanced chemical vapor deposition process, over the silicon oxide layer 28. The method further includes forming an insulating layer 36 over the second nitride layer. The passivation layers of the invention is preferably formed over the top metal layer.