Patents by Inventor Yao-Feng Lin

Yao-Feng Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12288735
    Abstract: An exemplary semiconductor structure includes a device substrate having a first side and a second side. A dielectric layer is disposed over the first side of the device substrate. A through via extends along a first direction through the dielectric layer and through the device substrate from the first side to the second side. The through via has a total length along the first direction and a width along a second direction that is different than the first direction. The total length is a sum of a first length of the through via in the dielectric layer and a second length of the through via in the device substrate. The first length is less than the second length. A guard ring is disposed in the dielectric layer and around the through via.
    Type: Grant
    Filed: June 6, 2022
    Date of Patent: April 29, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
    Inventors: Min-Feng Ku, Yao-Chun Chuang, Cheng-Chien Li, Ching-Pin Lin
  • Publication number: 20250076369
    Abstract: A minimum IC operating voltage searching method includes acquiring a corner type of an IC, acquiring ring oscillator data of the IC, generating a first prediction voltage according to the corner type and the ring oscillator data by using a training model, generating a second prediction voltage according to the ring oscillator data by using a non-linear regression approach under an N-ordered polynomial, and generating a predicted minimum IC operating voltage according to the first prediction voltage and the second prediction voltage. N is a positive integer.
    Type: Application
    Filed: April 16, 2024
    Publication date: March 6, 2025
    Applicant: MEDIATEK INC.
    Inventors: Ronald Kuo-Hua Ho, Kun-Yu Wang, Yen-Chang Shih, Sung-Te Chen, Cheng-Han Wu, Yi-Ying Liao, Chun-Ming Huang, Yen-Feng Lu, Ching-Yu Tsai, Tai-Lai Tung, Kuan-Fu Lin, Bo-Kang Lai, Yao-Syuan Lee, Tsyr-Rou Lin, Ming-Chao Tsai, Li-Hsuan Chiu
  • Patent number: 12237261
    Abstract: A semiconductor device includes an insulating layer, wherein the insulating layer has a via opening and a conductive line opening. The semiconductor device further includes a via in the via opening. The semiconductor device further includes a conductive line in the conductive line opening. The conductive line includes a first liner layer, wherein a first thickness of the first liner layer over the via is less than a second thickness of the first liner layer over the insulating layer, and a conductive fill, wherein the first liner layer surrounds the conductive fill.
    Type: Grant
    Filed: May 4, 2023
    Date of Patent: February 25, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shu-Cheng Chin, Yao-Min Liu, Hung-Wen Su, Chih-Chien Chi, Chi-Feng Lin
  • Patent number: 12230549
    Abstract: Three-dimensional integrated circuit (3DIC) structures and methods of forming the same are provided. A 3DIC structure includes a semiconductor package, a first package substrate, a molded underfill layer and a thermal interface material. The semiconductor package is disposed over and electrically connected to the first package substrate through a plurality of first bumps. The semiconductor package includes at least one semiconductor die and an encapsulation layer aside the semiconductor die. The molded underfill layer surrounds the plurality of first bumps and a sidewall of the semiconductor package, and has a substantially planar top surface. The CTE of the molded underfill layer is different from the CTE of the encapsulation layer of the semiconductor package. The thermal interface material is disposed over the semiconductor package.
    Type: Grant
    Filed: April 11, 2022
    Date of Patent: February 18, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Min Lin, Ching-Hua Hsieh, Chih-Wei Lin, Sheng-Hsiang Chiu, Sheng-Feng Weng, Yao-Tong Lai
  • Publication number: 20090257752
    Abstract: A method for operating a network device is provided. The method comprises steps of providing a first transceiver to establish a first link via a first medium; providing a second transceiver to establish a second link via a second medium; and enabling one of the first and the second transceivers to establish a corresponding one of the first and second links according to a predetermined order, wherein a media access controller transmits a first datum via the first medium by using the first link, and transmits a second datum via the second medium by using the second link.
    Type: Application
    Filed: April 14, 2009
    Publication date: October 15, 2009
    Applicant: REALTEK SEMICONDUCTOR CORP.
    Inventors: Ming-Yuh Yeh, Wei-Po Wang, Po-Wei Liu, Yao-Feng Lin, Shih-Hsuan Chiu