Abstract: Systems and methods for monitoring copper corrosion in an integrated circuit (IC) device are disclosed. A corrosion-sensitive structure formed in the IC device may include a p-type active region adjacent an n-type active region to define a p-n junction space charge region. A copper region formed over the silicon may be connected to both the p-region and n-region by respective contacts, to thereby define a short circuit. Light incident on the p-n junction space charge region, e.g., during a CMP process, creates a current flow through the metal region via the short circuit, which drives chemical reactions that cause corrosion in the copper region. Due to the short circuit configuration, the copper region is highly sensitive to corrosion. The corrosion-sensitive structure may be arranged with less corrosion-sensitive copper structures in the IC device, with the corrosion-sensitive structure used as a proxy to monitor for copper corrosion in the IC device.

Abstract: Resistive random access memory (RRAM) cells, for example conductive bridging random access memory (CBRAM) cells and oxygen vacancy-based RRAM (OxRRAM) cells are provided. An RRAM cell may include a metal-insulator-metal (MIM) structure formed between adjacent metal interconnect layers or between a silicided active layer (e.g., including MOSFET devices) and a first metal interconnect layer. The MIM structure of the RRAM cell may be formed by a damascene process including forming a tub opening in a dielectric region, forming a cup-shaped bottom electrode in the tub opening, forming a cup-shaped insulator in an interior opening defined by the cup-shaped bottom electrode, and forming a top electrode in an interior opening defined by the cup-shaped insulator. The cup-shaped bottom electrode, or a component thereof (in the case of a multi-layer bottom electrode) may be formed concurrently with interconnect vias, e.g., by deposition of tungsten or other conformal metal.

Abstract: A metal-insulator-metal (MIM) capacitor includes a bottom electrode cup, an insulator cup, and a top electrode. The bottom electrode cup includes a laterally-extending bottom electrode cup base, and a bottom electrode cup sidewall extending upwardly from the laterally-extending bottom electrode cup base. The insulator cup is formed in an opening defined by the bottom electrode cup, and includes a laterally-extending insulator cup base formed over the laterally-extending bottom electrode cup base, and an insulator cup sidewall extending upwardly from the laterally-extending insulator cup base. A dielectric sidewall spacer is located between the insulator cup sidewall and the bottom electrode cup sidewall. The top electrode is formed in an opening defined by the insulator cup.

Abstract: A metal-insulator-metal (MIM) capacitor includes a bottom electrode cup, an insulator, and a top electrode. The bottom electrode cup includes a laterally-extending bottom electrode cup base and a bottom electrode cup sidewall extending upwardly from the laterally-extending bottom electrode cup base. The insulator includes an insulator cup formed in an opening defined by the bottom electrode cup, and a rounded insulator flange extending laterally outwardly and curving upwardly from the insulator cup, the rounded insulator flange covering an upper surface of the bottom electrode cup sidewall. The top electrode is formed in an opening defined by the insulator cup. The top electrode is insulated from the upper surface of the bottom electrode cup sidewall by the rounded insulator flange.

Abstract: Resistive random access memory (RRAM) cells, for example conductive bridging random access memory (CBRAM) cells and oxygen vacancy-based RRAM (OxRRAM) cells are provided. An RRAM cell may include a metal-insulator-metal (MIM) structure formed between adjacent metal interconnect layers or between a silicided active layer (e.g., including MOSFET devices) and a first metal interconnect layer. The MIM structure of the RRAM cell may be formed by a damascene process including forming a tub opening in a dielectric region, forming a cup-shaped bottom electrode in the tub opening, forming a cup-shaped insulator in an interior opening defined by the cup-shaped bottom electrode, and forming a top electrode in an interior opening defined by the cup-shaped insulator. The cup-shaped bottom electrode, or a component thereof (in the case of a multi-layer bottom electrode) may be formed concurrent with interconnect vias, e.g., by deposition of tungsten or other conformal metal.

Abstract: A method for making a three dimensional (3D) Metal-Insulator-Metal (MIM) capacitor and trenches by etching a dielectric layer to form a via or contact hole, a tub, and a trench in the dielectric layer; depositing conformal metal in the via or contact hole, the tub, and the trench, wherein the deposited conformal metal forms bottom and sidewall portions of a 3D bottom electrode of a metal-insulator-metal (MIM) capacitor in the tub, and wherein the deposited conformal metal forms a via or contact in the via or contact hole; removing conformal metal and at least a portion of the dielectric layer from a lip of the tub; depositing an insulator layer on the 3D bottom electrode to form an insulator layer of the MIM capacitor; and depositing a metal layer on the insulator layer to form a top electrode of the MIM capacitor.

Abstract: A method for making a metal-insulator-metal (MIM) capacitors by etching a dielectric layer to form a via or contact hole, a tub, and a trench in the dielectric layer; depositing conformal metal in the via or contact hole, the tub, and the trench, wherein deposited conformal metal forms a via or contact in the via or contact hole; depositing a bottom electrode metal in the tub to form a bottom electrode of a metal-to-metal (MIM) capacitor; removing bottom electrode metal from the bottom electrode to form a dish-shape upper surface; depositing an insulator material on the bottom electrode to form an insulator layer of the MIM capacitor; and depositing a top electrode metal on the insulator layer to form a top electrode of the MIM capacitor.

Abstract: Ferroelectric random access memory (FRAM) capacitors and methods of forming FRAM capacitors are provided. An FRAM capacitor may be formed between adjacent metal interconnect layers or between a silicided active layer (e.g., including MOSFET devices) and a first metal interconnect layer. The FRAM capacitor may be formed by a damascene process including forming a tub opening in a dielectric region, forming a cup-shaped bottom electrode, forming a cup-shaped ferroelectric element in an interior opening defined by the cup-shaped bottom electrode, and forming a top electrode in an interior opening defined by the cup-shaped ferroelectric element. The FRAM capacitor may form a component of an FRAM memory cell. For example, an FRAM memory cell may include one FRAM capacitor and one transistor (1T1C configuration) or two FRAM capacitors and two transistor (2T2C configuration).

Abstract: An integrated circuit package module includes an integrated circuit package device including a contact element, and a bonding system formed on the integrated circuit package device. The bonding system includes a bonding system substrate and a bonding element formed in the bonding system substrate and conductively coupled to the contact element of the integrated circuit package device. The bonding element includes (a) a conduction component conductively connected to the contact element, the conduction component formed from a first metal having a first melting point, and (b) a bonding component formed from a second metal having a second melting point lower than the first melting point of the first metal.

Abstract: A method of forming a partially silicided element is provided. A silicided structure including a silicide layer on a base structure is formed. A dielectric region is formed over the silicided structure. The dielectric region is etched to form a contact opening exposing a first area of the silicide layer and a tub opening exposing a second area of the silicide layer. A conformal metal is deposited to (a) fill the contact opening to define a contact and (b) form a cup-shaped metal structure in the tub opening. Another etch is performed to remove the cup-shaped metal structure in the tub opening, to remove the underlying silicide layer second area and to expose an underlying area of the base structure, wherein the silicide layer first area remains intact. The base structure with the intact silicide layer first area and removed silicide layer second area defines the partially silicided element.

Abstract: An integrated resistor includes a resistor tub, a resistive element, and a dielectric liner. The resistor tub is formed from a conformal metal, and includes a laterally-extending tub base and vertically-extending tub sidewalls extending upwardly from the laterally-extending tub base, wherein the laterally-extending tub base and vertically-extending tub sidewalls define in a resistor tub interior opening. The dielectric liner is formed in the resistor tub interior opening. The resistive element is formed over the dielectric liner in the resistor tub interior opening, and includes a pair of resistor heads connected by a laterally-extending resistor body. The dielectric liner electrically insulates the resistive element from the resistor tub.

Abstract: A multi-capacitor module includes a stacked metal-insulator-metal (MIM) structure including a cup-shaped first electrode, a cup-shaped first insulator formed over the cup-shaped first electrode, a cup-shaped second electrode formed over the cup-shaped first insulator, a cup-shaped second insulator formed over the cup-shaped second electrode, a third electrode formed over the cup-shaped second insulator. The stacked MIM structure also includes a first sidewall spacer located between the cup-shaped first electrode and the cup-shaped second electrode, and a second sidewall spacer located between the cup-shaped second electrode and the third electrode. The cup-shaped first electrode, the cup-shaped second electrode, and the cup-shaped first insulator define a first capacitor, and the cup-shaped second electrode, the third electrode, and the cup-shaped second insulator define a second capacitor.

Abstract: A multi-capacitor module includes a nested metal-insulator-metal (MIM) structure including a cup-shaped first electrode, a cup-shaped first insulator formed over the cup-shaped first electrode, a cup-shaped second electrode formed over the cup-shaped first insulator, a cup-shaped second insulator formed over the cup-shaped second electrode, and a third electrode formed over the cup-shaped second insulator. The cup-shaped first electrode, the cup-shaped second electrode, and the cup-shaped first insulator define a first capacitor, and the cup-shaped second electrode, the third electrode, and the cup-shaped second insulator define a second capacitor physically nested in the first capacitor.

Abstract: A system includes a metal tub structure formed in an integrated circuit (IC) structure, a first metal component, and a second metal component. The first metal component is formed from a first metal. The first metal component is formed in an opening defined by the metal tub structure, and includes a first metal first junction element, a first metal second junction element, and a first metal bridge electrically connected to the first metal first junction element and the first metal second junction element. The second metal component is formed from a second metal different than the first metal, and includes a second metal first junction element electrically connected to the first metal first junction element to define a first thermocouple junction, and a second metal second junction element electrically connected to the first metal second junction element to define a second thermocouple junction.

Abstract: A metal-insulator-metal (MIM) capacitor includes a bottom electrode, an insulator cup formed on the bottom electrode, a top electrode formed in an opening defined by the insulator cup, a top electrode connection element electrically connected to the top electrode, a vertically-extending bottom electrode contact electrically connected to the bottom electrode, and a bottom electrode connection element electrically connected to the vertically-extending bottom electrode contact. The bottom electrode is formed in a lower metal layer. The insulator cup is formed in a tub opening in a dielectric region and includes a laterally extending insulator cup base formed on the bottom electrode and a vertically-extending insulator cup sidewall extending upwardly from the laterally extending insulator cup base. The top electrode connection element and bottom electrode connection element are formed in an upper metal layer.

Abstract: A thin-film resistor (TFR) module is formed in an integrated circuit device. The TFR module includes a pair of metal TFR heads (e.g., copper damascene trench structures), a TFR element formed directly on the metal TFR heads to define a conductive path between the pair of TFR heads through the TFR element, and TFR contacts connected to the TFR heads. The TFR heads may be formed in a metal interconnect layer, along with various interconnect elements of the integrated circuit device. The TFR element may be formed by depositing and patterning a TFR element/diffusion barrier layer over the TFR heads and interconnect elements formed in the metal interconnect layer. The TFR element may be formed from a material that also provides a barrier against metal diffusion (e.g., copper diffusion) from each metal TFR head and interconnect element. For example, the TFR element may be formed from tantalum nitride (TaN).

Abstract: A thin film resistor (TFR) module may be formed in copper interconnect in an integrated circuit device. A pair of displacement-plated TFR heads may be formed by forming a pair of copper TFR head elements (e.g., damascene trench elements) spaced apart from each other in a dielectric region, and displacement plating a barrier region on each TFR head element to form a displacement-plated TFR head. A TFR element may be formed on the pair of displacement-plated TFR heads to define a conductive path between the pair of TFR head elements through the TFR element and through the displacement-plated barrier region on each metal TFR head. Conductive contacts may be formed connected to the pair of displacement-plated TFR heads. The displacement-plated barrier regions may protect the copper TFR heads from copper corrosion and/or diffusion, and may comprise CoWP, CoWB, Pd, CoP, Ni, Co, Ni—Co alloy, or other suitable material.

Abstract: A thin film resistor (TFR) module includes a metal cup structure, a dielectric liner region, a TFR element, and a pair of TFR heads electrically connected to the TFR element. The metal cup structure includes a laterally-extending metal cup base and multiple metal cup sidewalls extending upwardly from the laterally-extending metal cup base. The dielectric liner region is formed in an opening defined by the metal cup structure. The TFR element is formed in an opening defined by the dielectric liner region, wherein the TFR element is insulated from the metal cup structure by the dielectric liner region.

Abstract: An array of metal-oxide-metal (MOM) capacitors formed in an integrated circuit (IC) structure may be used for evaluating misalignments between patterned layers of the IC structure. The array of MOM capacitors may be formed in a selected set of patterned layers, e.g., a via layer formed between a pair of metal interconnect layers. The MOM capacitors may be programmed with different patterned layer alignments (e.g., built in to photomasks or reticles used to form the patterned layers) to define an array of different alignments. When the MOM capacitors are formed on the wafer, the actual patterned layer alignments capacitors may differ from the programmed layer alignments due a process-related misalignment. The MOM capacitors may be subjected to electrical testing to identify this process-related misalignment, which may be used for initiating a correcting action, e.g., adjusting a manufacturing process or discarding misaligned IC structures or devices.

Abstract: A system-on-chip may include an inductor-capacitor oscillator monolithically integrated into the system-on-chip The inductor-capacitor oscillator may be configured to improve frequency stability and reduce noise when compared to a resistor-capacitor oscillator. Methods of making integrated oscillators may involve forming an inductor at least partially while forming a BEOL structure on a substrate. A capacitor supported on and/or embedded within the semiconductor material of the substrate may be formed before or while forming the BEOL structure. The inductor may be connected to the capacitor in parallel at least partially utilizing the BEOL structure to form an integrated inductor-capacitor oscillator.