Abstract: The present invention provides a dual-substrate antenna package structure and a method for manufacturing the same. The package structure includes a main substrate and at least one antenna substrate. The antenna substrate is provided on a pad of the main substrate by an array of solder balls placed on the antenna substrate, at least one chip is electrically connected to the main substrate, and metal wiring provided on the main substrate electrically connects the pad to the chip. The array of solder balls includes support solder balls and conventional solder balls, and the support solder balls have a melting point high than 250° C. A spacing distance between the antenna substrate and the main substrate can be kept stable during the reflow soldering process and subsequent processes because the support solder balls having the high melting point can always maintain the stability of the structure during the reflow soldering process.

Abstract: The present application discloses a double-sided SiP packaging structure and a manufacturing method thereof, wherein the double-sided SiP packaging structure comprises a substrate, a first packaging structure arranged on the substrate, and a second packaging structure arranged below the substrate; the second packaging structure comprises a chip, interposer and a molding material; a conductive structure array is arranged on an upper surface of the interposer; the interposer is arranged below the substrate through the conductive structure array; a space region among a lower surface of the substrate, the chip and the interposer is filled with the molding material; a conductive bonding pad array is arranged on the lower surface of the interposer; and a groove is formed in a part of region between the conductive bonding pad and an edge contour of the interposer.

Abstract: A semiconductor device has a carrier with a fixed size. A plurality of first semiconductor die is singulated from a first semiconductor wafer. The first semiconductor die are disposed over the carrier. The number of first semiconductor die on the carrier is independent from the size and number of first semiconductor die singulated from the first semiconductor wafer. An encapsulant is deposited over and around the first semiconductor die and carrier to form a reconstituted panel. An interconnect structure is formed over the reconstituted panel while leaving the encapsulant devoid of the interconnect structure. The reconstituted panel is singulated through the encapsulant. The first semiconductor die are removed from the carrier. A second semiconductor die with a size different from the size of the first semiconductor die is disposed over the carrier. The fixed size of the carrier is independent of a size of the second semiconductor die.

Abstract: A semiconductor device has a first RDL substrate with first conductive pillars formed over a first surface of the first RDL substrate. A first electrical component is disposed over the first surface of the first RDL substrate. A hybrid substrate is bonded to the first RDL substrate. An encapsulant is deposited around the hybrid substrate and first RDL substrate with the first conductive pillars and first electrical component embedded within the encapsulant. A second RDL substrate with second conductive pillars formed over the second RDL substrate and second electrical component disposed over the second RDL substrate can be bonded to the hybrid substrate. A second RDL can be formed over a second surface of the first RDL substrate. A third electrical component is disposed over a second surface of the first RDL substrate. A shielding frame is disposed over the third electrical component.

Abstract: A semiconductor device has an RDL substrate and hybrid substrate with a plurality of bumps. The hybrid substrate is bonded to the RDL substrate. An encapsulant is deposited around the hybrid substrate and RDL substrate with the bumps embedded within the encapsulant. The hybrid substrate has a core substrate, first RDL formed over a first surface of the core substrate, conductive pillars formed over the first RDL, and second RDL over a second surface of the core substrate. A portion of the encapsulant is removed to expose the conductive pillars. The RDL substrate has a carrier and RDL formed over a surface of the carrier. The carrier is removed after bonding the hybrid substrate to the RDL substrate. Alternatively, the RDL substrate has a core substrate, first RDL formed over a first surface of the core substrate, and second RDL formed over a second surface of the core substrate.

Abstract: An integrated package and a method for making the same are provided. The integrated package includes: a molded substrate having a top substrate surface and a bottom substrate surface; a semiconductor chip embedded in the molded substrate; a bottom antenna structure disposed on the bottom substrate surface and electrically connected to the semiconductor chip; and an antenna package embedded in the molded substrate, and including: an antenna package substrate; and a top antenna structure disposed on the antenna package substrate and configured for coupling electromagnetic energy with the bottom antenna structure.

Abstract: A semiconductor device has a first hybrid substrate with a first thickness, and a second hybrid substrate with a second thickness different from the first thickness of the first hybrid substrate. An encapsulant is deposited around the first hybrid substrate and second hybrid substrate. A portion of the first hybrid substrate and a portion of the second hybrid substrate and a portion of the encapsulant can be removed after encapsulation to achieve uniform thickness for the first hybrid substate and second hybrid substrate. The first hybrid substrate has an embedded substrate, a first interconnect structure formed over a first surface of the embedded substrate, and a second interconnect structure formed over a second surface of the embedded substrate opposite the first surface of the embedded substrate. A plurality of conductive pillars is formed over the first interconnect structure. A plurality of conductive vias is formed through the embedded substrate.

Abstract: The present invention provides a package structure with an inductor and a manufacturing method thereof, the inductor and the interconnection component are used as n second package module, and stacked with other components such as the first package module to form a stack-like package structure. The first package module is provided with other electronic elements. Then the first and second package modules can be synchronously subjected to package manufacturing, which improves the production efficiency. Additionally, the soldering balls with different heights are formed on the first faces of the interconnecting structural component and the inductive device by adjusting the consumption of soldering paste, which make the second faces of the inductor and the interconnection component are coplanar, then inductor with different heights can form a flat interconnecting plane, which makes the sequential process such as pasting and mounting can be conveniently performed.

Abstract: The present invention provides a package structure and a method for manufacturing the same. The package structure includes at least two electrical elements, a second reconstruction layer, and a metal lead frame, wherein at least one of the electrical elements is a chip, at least one of the electrical elements has a first reconstruction layer, and the second reconstruction layer has a smaller pin pitch than that of the metal lead frame; the second reconstruction layer has a first surface and a second surface, a functional surface of the electrical element is disposed on and connected to the first surface, and at least one of the electrical elements is connected to the second reconstruction layer; and the second surface is disposed on and connected to the metal lead frame. A fan-out package structure is formed on the metal lead frame, which improves the heat dissipation capacity of the chip.

Abstract: The present invention provides an antenna packaging structure and a manufacturing method thereof. An antenna and a chip are respectively disposed on two sides of a substrate layer, antenna layers are formed by an antenna support member, a first antenna layer located above the antenna support member and a second antenna layer located below the antenna support member together, and interlayer dielectrics of the antenna support member and the antenna layers are low dielectric loss materials, so that a heterogeneous and isomerous antenna structure is formed, thereby reducing the problems such as current leakage and stray capacitance in the packaging structure caused by dielectric loss, and reducing a size of the antenna packaging structure.

Abstract: The present invention provides an antenna packaging structure and a manufacturing method thereof. An antenna and a chip are respectively disposed on two sides of a substrate layer, antenna layers are formed by an antenna support member, a first antenna layer located above the antenna support member and a second antenna layer located below the antenna support member together, and interlayer dielectrics of the antenna support member and the antenna layers are low dielectric loss materials, so that a heterogeneous and isomerous antenna structure is formed, thereby reducing the problems such as current leakage and stray capacitance in the packaging structure caused by dielectric loss, and reducing a size of the antenna packaging structure.

Abstract: The present invention provides a fan-out packaging structure and a manufacturing method thereof. The packaging structure includes a redistribution layer, at least one plastic packaging layer, at least one first shielding layer, at least one chip, and at least one electrical connector. The redistribution layer includes a grounding line layer, and the chip and the electrical connector are disposed on a first face of the redistribution layer and are electrically connected to the redistribution layer; the plastic packaging layer encapsulates the electrical connector and the chip; the first shielding layer at least covers a side face of the plastic packaging layer; and the electrical connector is at least partially exposed to the side face of the plastic packaging layer and electrically connected to the first shielding layer.

Abstract: The present invention provides a packaging structure and a manufacturing method thereof. The packaging structure includes an interposer, chips, and warpage adjustment structures, wherein the interposer includes a first surface and a second surface opposite thereto, and the chips are electrically connected to the first surface of the interposer; the warpage adjustment structures are symmetrically distributed with respect to a center of the first surface; and each of the warpage adjustment structures include a warpage adjustment piece and/or a cavity filled with a plastic packaging material, the warpage adjustment piece is disposed on the first surface, and the cavity is located outside conducting structures and sinks inward along the first surface. By cooperation between the warpage adjustment pieces and the cavities filled with the plastic packaging material, the warpage of the interposer in horizontal and vertical directions can be reduced.

Abstract: A semiconductor device has an interposer mounted over a carrier. The interposer includes TSV formed either prior to or after mounting to the carrier. An opening is formed in the interposer. The interposer can have two-level stepped portions with a first vertical conduction path through a first stepped portion and second vertical conduction path through a second stepped portion. A first and second semiconductor die are mounted over the interposer. The second die is disposed within the opening of the interposer. A discrete semiconductor component can be mounted over the interposer. A conductive via can be formed through the second die or encapsulant. An encapsulant is deposited over the first and second die and interposer. A portion of the interposer can be removed to that the encapsulant forms around a side of the semiconductor device. An interconnect structure is formed over the interposer and second die.

Abstract: The present invention provides a packaging structure and a manufacturing method thereof. The packaging structure includes a lower package, an upper package and a first redistribution stack layer disposed between the lower package and the upper package, wherein the first redistribution stack layer is electrically connected to the lower package and the upper package; the lower package includes a prefabricated substrate and a first plastic packaging layer surrounding the periphery of the prefabricated substrate; and the minimum line width/line spacing of the first redistribution stack layer is less than the minimum line width/line spacing of the prefabricated substrate. The lower package includes the prefabricated substrate and the first redistribution stack layer is disposed above the prefabricated substrate and has the minimum line width/line spacing less than that of the prefabricated substrate, so that more chips and/or device packages are integrated in the packaging structure.

Abstract: The present invention provides a packaging structure and a manufacturing method thereof. The packaging structure includes a lower package and an upper package; wherein the lower package includes a prefabricated interconnected silicon core stack structure which includes a silicon interconnection layer, and the silicon interconnection layer includes a first surface and a second surface; a back-end redistribution stack layer and a first prefabricated redistribution stack layer are stacked on the first surface and in electrical connection; a passivation layer is disposed on the second surface; the silicon interconnection layer includes a silicon substrate and several first prefabricated conductive pillars, each first prefabricated conductive pillar includes a first end and a second end, the first end is exposed from the first surface, and the second end is exposed from a side of the passivation layer; and the upper package is disposed above the first prefabricated redistribution stack layer.

Abstract: The present invention provides a packaging structure and a manufacturing method thereof. The packaging structure includes: a lower package, an upper package disposed above the lower package, and a first redistribution stack layer that is disposed between the lower package and the upper package and is electrically connected to the lower package and the upper package. The lower package includes a first prefabricated redistribution stack layer and a first plastic packaging layer surrounding the first prefabricated redistribution stack layer. A minimum line width and line spacing of at least one first prefabricated conductive layer in the first prefabricated redistribution stack layer is less than a minimum line width and line spacing of at least one first conductive layer in the first redistribution stack layer.

Abstract: The present invention discloses a fan-out package structure. The fan-out package structure includes: a redistribution layer, a solder ball disposed below the redistribution layer, a high-heat chip and a low-heat chip that are electrically connected above the redistribution layer, and a plastic package material disposed above the redistribution layer in a filling manner and coating the high-heat chip and the low-heat chip, wherein an upper surface of the high-heat chip is exposed outside the plastic package material, and an upper surface of the low-heat chip is encapsulated in the plastic package material; a warpage adjusting and protective layer is disposed on the upper surface of the low-heat chip, or at least one through hole is formed in the plastic package material right above the low-heat chip and part of the upper surface of the low-heat chip is exposed outside the plastic package material through the through hole.

Abstract: A semiconductor device has a substrate with first and second conductive layers formed over first and second opposing surfaces of the substrate. A plurality of bumps is formed over the substrate. A semiconductor die is mounted to the substrate between the bumps. An encapsulant is deposited over the substrate and semiconductor die. A portion of the bumps extends out from the encapsulant. A portion of the encapsulant is removed to expose the substrate. An interconnect structure is formed over the encapsulant and semiconductor die and electrically coupled to the bumps. A portion of the substrate can be removed to expose the first or second conductive layer. A portion of the substrate can be removed to expose the bumps. The substrate can be removed and a protection layer formed over the encapsulant and semiconductor die. A semiconductor package is disposed over the substrate and electrically connected to the substrate.

Abstract: A semiconductor device has a semiconductor die. A first contact pad, second contact pad, and third contact pad are formed over the semiconductor die. An under-bump metallization layer (UBM) is formed over the first contact pad, second contact pad, and third contact pad. The UBM electrically connects the first contact pad to the second contact pad. The third contact pad is electrically isolated from the UBM. Conductive traces can be formed extending between the first contact pad and second contact pad under the UBM. A fourth contact pad can be formed over the first contact pad and a fifth contact pad can be formed over the second contact pad. The UBM is then formed over the fourth and fifth contact pads.