Abstract: A semiconductor device has a first hybrid substrate with a first thickness, and a second hybrid substrate with a second thickness different from the first thickness of the first hybrid substrate. An encapsulant is deposited around the first hybrid substrate and second hybrid substrate. A portion of the first hybrid substrate and a portion of the second hybrid substrate and a portion of the encapsulant can be removed after encapsulation to achieve uniform thickness for the first hybrid substate and second hybrid substrate. The first hybrid substrate has an embedded substrate, a first interconnect structure formed over a first surface of the embedded substrate, and a second interconnect structure formed over a second surface of the embedded substrate opposite the first surface of the embedded substrate. A plurality of conductive pillars is formed over the first interconnect structure. A plurality of conductive vias is formed through the embedded substrate.

Abstract: A semiconductor device has an integrated passive device (IPD) wafer including an IPD formed on the IPD wafer. A semiconductor die is mounted on the IPD wafer. An interconnect structure is mounted on the IPD wafer. The IPD wafer is singulated to provide an IPD die with the IPD, semiconductor die, and interconnect structure. An encapsulant is deposited over the IPD die with the interconnect structure exposed from the encapsulant. A shielding layer is formed over the encapsulant.

Abstract: A semiconductor device has a first semiconductor die and a modular interconnect structure adjacent to the first semiconductor die. An encapsulant is deposited over the first semiconductor die and modular interconnect structure as a reconstituted panel. An interconnect structure is formed over the first semiconductor die and modular interconnect structure. An active area of the first semiconductor die remains devoid of the interconnect structure. A second semiconductor die is mounted over the first semiconductor die with an active surface of the second semiconductor die oriented toward an active surface of the first semiconductor die. The reconstituted panel is singulated before or after mounting the second semiconductor die. The first or second semiconductor die includes a microelectromechanical system. The second semiconductor die includes an encapsulant and an interconnect structure formed over the second semiconductor die.

Abstract: The present invention discloses a package structure and a method for forming the same. The package structure includes a substrate, a chip, a first plastic package layer and a support block, wherein the substrate includes a first surface and a second surface; the chip is disposed on the first surface; the first plastic package layer is disposed on the first surface and packages the chip; the support block is disposed on the second surface; and in a thickness direction of the substrate, an overlapping region exists between the chip and the support block, and a thermal expansion coefficient of the chip is equal to a thermal expansion coefficient of the support block. The support block can counteract part of stress to avoid problems such as warping or twisting. Due to the overlapping region, a counteraction function of the support block on the stress exerted on the chip can be improved.

Abstract: A semiconductor device has a first interconnect structure. A pre-molded bridge die is disposed over the first interconnect structure. An encapsulant is deposited over the pre-molded bridge die. A second interconnect structure is disposed over the encapsulant and pre-molded bridge die. A first semiconductor die is disposed over the second interconnect structure within a footprint of the pre-molded bridge die. A second semiconductor die is disposed over the second interconnect structure within the footprint of the pre-molded bridge die.

Abstract: A semiconductor device has an electrical component and a first interconnect structure disposed adjacent to the electrical component. The electrical component can be a direct metal bonded semiconductor die or a flipchip semiconductor die. The first interconnect structure can be an interposer unit or a conductive pillar. A split antenna is disposed over the electrical component and first interconnect structure. The split antenna has a first antenna section and a second antenna section with an adhesive material disposed between the first antenna section and second antenna section. A second interconnect structure is formed over the electrical component and first interconnect structure. The second interconnect structure has one or more conductive layers and insulating layers. The first interconnect structure and second interconnect structure provide a conduction path between the electrical component and split antenna. An encapsulant is deposited around the electrical component and first interconnect structure.

Abstract: A semiconductor device has a first interconnect structure. A first bridge die is disposed over the first interconnect structure. An encapsulant is deposited over the first bridge die. A second interconnect structure is formed over the first bridge die and encapsulant. A second bridge die is disposed over the second interconnect structure.

Abstract: An integrated package and a method for making the same are provided. The integrated package includes: an antenna module including: an antenna module substrate; and a top antenna structure disposed on the antenna module substrate; a first encapsulant encapsulating the antenna module; a first redistribution structure disposed on a bottom surface of the first encapsulant, wherein the first redistribution structure includes a bottom antenna structure configured for coupling electromagnetic energy with the top antenna structure; and a semiconductor chip mounted on a bottom surface of the first redistribution structure and electrically coupled with the bottom antenna structure.

Abstract: A semiconductor device has a pre-molded discrete electrical component and a first encapsulant deposited over the pre-molded discrete electrical component. A first conductive layer is formed over the first encapsulant and pre-molded discrete electrical component. An electrical component is disposed over the first conductive layer. A second encapsulant is deposited over the electrical component and first conductive layer. A second conductive layer is formed over the second encapsulant. A conductive pillar is formed between the first conductive layer and second conductive layer through the second encapsulant. The pre-molded discrete electrical component has a discrete component and a third encapsulant deposited around the discrete component. The discrete component has an electrical terminal, a finish formed over the electrical terminal, and a third conductive layer formed over the finish.

Abstract: The present invention provides an SIP package structure. The SIP package structure comprises a first module, a second module and a shielding assembly, wherein the first module and the second module are horizontally distributed or vertically stacked; electromagnetic sensitive frequencies of the first module and the second module are different; the shielding assembly comprises a first shielding structure covering the first module and a second shielding structure covering the second module; and at least part of the first shielding structure and/or at least part of the second shielding structure are/is disposed between the first module and the second module.

Abstract: The present disclosure relates to a package structure and a method for forming the same. The package structure includes: a first surface and a second surface that are opposite, passive devices mounted on the first surface of the substrate; a first molding layer encapsulating the passive devices and covering the first surface of the substrate; a first chip comprising a back face and a functional face that are opposite; metal connection structures each comprising a horizontal metal strip and a vertical metal pin electrically connected to the horizontal metal strip; a second molding layer encapsulating the metal connection structures and the first chip and covering the second surface of the substrate; and first solder bumps on the exposed top surfaces of the external terminals.

Abstract: The present disclosure relates to a package structure and a method for forming the same. The package structure includes: a plurality of second interconnect metal traces and bonding pads in a same plane; a plurality of first surface metal bumps and first interconnect metal traces disposed on the first surfaces of the second interconnect metal traces; a plurality of passive devices correspondingly mounted on top surfaces of the first surface metal bumps; a first molding layer encapsulating the passive devices, the first surface metal bumps, and the first interconnect metal traces, and covering the first surfaces of the bonding pads; a dielectric layer covering the second surfaces of the second interconnect metal traces and a bottom surface of the first molding layer; a first chip having wire bonding pads; and metal wires electrically connecting the wire bonding pads to the second surfaces of the bonding pads.

Abstract: A semiconductor device has an electrical component and a plurality of e-bar structures disposed adjacent to the electrical component. An antenna interposer is disposed over a first surface of the e-bar structures. A redistribution layer is formed over a second surface of the e-bar structures opposite the first surface of the e-bar structures. The redistribution layer has a conductive layer and an insulating layer formed over the conductive layer. An encapsulant is deposited over the electrical component. The antenna interposer has a first conductive layer, an insulating layer formed over the first conductive layer, and a second conductive layer formed over the insulating layer. The second conductive layer can be arranged as a plurality of islands or in a serpentine pattern.

Abstract: The present invention provides a fan-out package structure and a method for manufacturing the same. The fan-out package structure includes at least one chip and at least one redistribution layer on a functional surface side of the chip, and the redistribution layer includes a dielectric layer and a metal wiring layer distributed within the dielectric layer. The fan-out package structure further includes at least one dummy wafer on the redistribution layer, and the dummy wafer is insulated from the chip and in contact with the metal wiring layer. By providing the dummy wafer on the redistribution layer and configuring the dummy wafer to connect to the metal wiring layer, the dummy wafer can not only function to support the structure and suppress the warpage, but also form a continuous heat dissipation channel, thereby improving thermal management capability of the fan-out package structure.

Abstract: A semiconductor device includes a plurality of electrical components. A first encapsulant is deposited over the plurality of electrical components to form a module. The module is disposed adjacent to a semiconductor die. A second encapsulant is deposited over the semiconductor die and module. A build-up interconnect structure is formed over the second encapsulant, module, and semiconductor die.

Abstract: A front opening unified pod has a housing and a plurality of horizontal support members disposed within the housing and adapted to accommodate a plurality of semiconductor wafers or panels. The plurality of semiconductor wafers or panels have a different size or shape, such as circular and rectangular. A first one of the plurality of horizontal support members has a wing to support the plurality of different size or shape semiconductor wafers or panels. The plurality of horizontal support members has a first side horizontal support member, a second side horizontal support member, and a center horizontal support member disposed between the first side horizontal support member and the second side horizontal support member. The plurality of horizontal support members is insertable into the housing. One or more of the plurality of horizontal support members has an opening for laser identification.

Abstract: A semiconductor device has a semiconductor die. A first contact pad, second contact pad, and third contact pad are formed over the semiconductor die. An under-bump metallization layer (UBM) is formed over the first contact pad, second contact pad, and third contact pad. The UBM electrically connects the first contact pad to the second contact pad. The third contact pad is electrically isolated from the UBM. Conductive traces can be formed extending between the first contact pad and second contact pad under the UBM. A fourth contact pad can be formed over the first contact pad and a fifth contact pad can be formed over the second contact pad. The UBM is then formed over the fourth and fifth contact pads.

Abstract: A semiconductor device has a semiconductor wafer including a plurality of semiconductor die. An insulating layer is formed over the semiconductor wafer. A portion of the insulating layer is removed by LDA to expose a portion of an active surface of the semiconductor die. A first conductive layer is formed over a contact pad on the active surface of the semiconductor die. The semiconductor wafer is singulated to separate the semiconductor die. The semiconductor die is disposed over a carrier with the active surface of the semiconductor die offset from the carrier. An encapsulant is deposited over the semiconductor die and carrier to cover a side of the semiconductor die and the exposed portion of the active surface. An interconnect structure is formed over the first conductive layer. Alternatively, a MUF material is deposited over a side of the semiconductor die and the exposed portion of the active surface.

Abstract: A semiconductor device has a semiconductor die and an encapsulant deposited over the semiconductor die. A first conductive layer is formed with an antenna over a first surface of the encapsulant. A second conductive layer is formed with a ground plane over a second surface of the encapsulant with the antenna located within a footprint of the ground plane. A conductive bump is formed on the ground plane. A third conductive layer is formed over the first surface of the encapsulant. A fourth conductive layer is formed over the second surface of the encapsulant. A conductive via is disposed adjacent to the semiconductor die prior to depositing the encapsulant. The antenna is coupled to the semiconductor die through the conductive via. The antenna is formed with the conductive via between the antenna and semiconductor die. A PCB unit is disposed in the encapsulant.

Abstract: A semiconductor device has a semiconductor die. A first insulating layer is disposed over the semiconductor die. A first via is formed in the first insulating layer over a contact pad of the semiconductor die. A first conductive layer is disposed over the first insulating layer and in the first via. A second insulating layer is disposed over a portion of the first insulating layer and first conductive layer. An island of the second insulating layer is formed over the first conductive layer and within the first via. The first conductive layer adjacent to the island is devoid of the second insulating layer. A second conductive layer is disposed over the first conductive layer, second insulating layer, and island. The second conductive layer has a corrugated structure. A width of the island is greater than a width of the first via.