Abstract: A vector processing apparatus has a number of pipeline arithmetic units operating concurrently to execute a set of vector instructions dealing with vector elements. Stack registers are provided for each arithmetic unit to hold the vector instruction address, leading vector element position and vector register internal address, so that one of the exceptions that can be detected successively by several arithmetic units during the process of the vector instructions is selected on a priority basis through the comparison of information in the stack of the currently detected exception with information of exception detected previously.

Abstract: A vector processing apparatus comprises plural vector registers, plural vector arithmetic units, and data transfer circuits. The vector processing apparatus comprises plural vector processing units each having plural vector registers, at least one vector arithmetic unit and at least one data transfer circuit to designate the number of vector elements to be processed for each vector processing unit in executing one vector instruction, thereby carrying out the vector processings corresponding to the number of elements to be essentially processed as a whole.