Abstract: In certain aspects, a memory system includes a non-volatile memory device and a memory controller coupled to the non-volatile memory device. The non-volatile memory device includes a plurality of memory groups. Each of the memory groups includes a plurality of memory units. The memory controller is configured to perform at least one of a first wear-leveling process by swapping a first memory group of the memory groups and a second memory group of the memory groups based on a first group write count for the first memory group and a second group write count for the second memory group, or a second wear-leveling process by swapping a first memory unit of the memory units and a second memory unit of the memory units based on a first unit write count for the first memory unit and a second unit write count for the second memory unit.

Abstract: The present disclosure involves methods, apparatuses, and computer-readable storage media for media scan in a memory system. In one example, a method for a memory system includes receiving commands from a host coupled to the memory system, wherein the memory system includes a memory device, the memory device includes a memory cell array, and the memory cell array includes a number of memory cells. The method further includes performing operations on the memory device based on the commands. The method further includes scanning at least a group of memory cells of the memory cell array by performing a number of scans within a scan period among the operations.

Abstract: A memory system includes a memory device including memory cells, and a memory controller coupled to the memory device. A memory cell is configured to be programmed to one of a first state and a second state. The first state corresponds to a first bit, and the second state corresponds to a second bit. The memory controller is configured to receive first data including bits, the bits of the first data including the first bit and the second bit, in response to a second number of the second bit in the first data being larger than a first number of the first bit in the first data, perform a first flipping operation to the first data to obtain a second data including the bits, and store the second data to the memory device.

Abstract: Aspects of the disclosure are directed to a memory system that can include a controller and a memory coupled thereto, each memory cell of the memory is configured to store m-bit information, and the controller includes at least one of an exclusive OR circuit, an inverter and an access circuit. The controller is configured to receive n groups of logic page data, and generate, at different values of m and n, at least one group of logic page data selectively by at least one of the exclusive OR circuit, the inverter and the access circuit. The controller is further configured to transmit the m groups of logic page data to the memory to generate 2n different data states in the memory.

Abstract: A method for a memory system is disclosed. The memory system can include a memory controller and a memory device. The method can include receiving data that includes bits and is to be written into the memory device, counting a first bit number of the bits corresponding to a first state and a second bit number of the bits corresponding to the second state, and in response to the second bit number of the bits being larger than the first bit number of the bits, the flipping operation is performed.

Abstract: A method for a memory system is disclosed. The memory system can include a memory controller and a memory device. The method can include receiving data that includes bits and is to be written into the memory device, counting a first bit number of the bits corresponding to a first state and a second bit number of the bits corresponding to the second state, and in response to the second bit number of the bits being larger than the first bit number of the bits, the flipping operation is performed.

Abstract: The present disclosure involves methods, apparatuses, and computer-readable storage media for media scan in a memory system. In one example, a method for a memory system includes receiving commands from a host coupled to the memory system, wherein the memory system includes a memory device, the memory device includes a memory cell array, and the memory cell array includes a number of memory cells. The method further includes performing operations on the memory device based on the commands. The method further includes scanning at least a group of memory cells of the memory cell array by performing a number of scans within a scan period among the operations.

Abstract: In certain aspects, a memory system includes a non-volatile memory device and a memory controller coupled to the non-volatile memory device. The non-volatile memory device includes a plurality of memory groups. Each of the memory groups includes a plurality of memory units. The memory controller is configured to perform at least one of a first wear-leveling process by swapping a first memory group of the memory groups and a second memory group of the memory groups based on a first group write count for the first memory group and a second group write count for the second memory group, or a second wear-leveling process by swapping a first memory unit of the memory units and a second memory unit of the memory units based on a first unit write count for the first memory unit and a second unit write count for the second memory unit.

Abstract: In certain aspects, a method for operating a non-volatile memory device is provided. The non-volatile memory device includes memory units. A write count of a first memory unit of the memory units is determined. In response to the write count of the first memory unit reaching one of preset values, a flipped bit count (FBC) of a second memory unit of the memory units that is physically adjacent to the first memory unit is obtained. In response to the FBC of the second memory unit exceeding a threshold, the second memory unit is refreshed.

Abstract: Aspects of the disclosure are directed to a memory system that can include a controller and a memory coupled thereto, each memory cell of the memory is configured to store m-bit information, and the controller includes at least one of an exclusive OR circuit, an inverter and an access circuit. The controller is configured to receive n groups of logic page data, and generate, at different values of m and n, at least one group of logic page data selectively by at least one of the exclusive OR circuit, the inverter and the access circuit. The controller is further configured to transmit the m groups of logic page data to the memory to generate 2n different data states in the memory.

Abstract: Apparatus, for performing decoding tasks in a NAND Flash memory controller, includes a first task queue for queuing decoding tasks of a first priority, a second task queue for queuing decoding tasks of a second priority higher than the first priority, and control circuitry that, on receipt of portions of data for a plurality of decoding tasks, releases, from the first and second task queues, respective decoding tasks to operate on respective portions of data, according to priorities of the decoding tasks. First and second decoders operate under first and second decoding schemes that differ in speed or complexity. Input switching circuitry controllably connects each data channel to the first or second decoder. Decoder-done control circuitry selects output of the first or second decoder upon receipt of a decoder-done signal from the first or second decoder. Completed decoding tasks are queued in first and second task-done queues according to priority.

Abstract: Apparatus, for performing decoding tasks in a NAND Flash memory controller, includes a first task queue for queuing decoding tasks of a first priority, a second task queue for queuing decoding tasks of a second priority higher than the first priority, and control circuitry that, on receipt of portions of data for a plurality of decoding tasks, releases, from the first and second task queues, respective decoding tasks to operate on respective portions of data, according to priorities of the decoding tasks. First and second decoders operate under first and second decoding schemes that differ in speed or complexity. Input switching circuitry controllably connects each data channel to the first or second decoder. Decoder-done control circuitry selects output of the first or second decoder upon receipt of a decoder-done signal from the first or second decoder. Completed decoding tasks are queued in first and second task-done queues according to priority.