Patents by Inventor Yaoyu Pang
Yaoyu Pang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220285299Abstract: A semiconductor die may be coupled to a printed circuit board using a solder ball. The semiconductor die comprises a redistribution layer formed above a semiconductor chip, a polymer layer formed on the redistribution layer, and an Under Bump Metallurgy (UBM) layer formed on the polymer layer. The polymer layer comprises a plurality of vias, which electrically couple the UBM layer to the redistribution layer. The entire UBM layer may be deposited with a continuously flat upper surface for coupling to the solder ball. The plurality of vias may be positioned such that they are centered on a point that is not central to the UBM layer.Type: ApplicationFiled: May 19, 2022Publication date: September 8, 2022Applicant: Cirrus Logic International Semiconductor Ltd.Inventors: Yaoyu PANG, Steven A. ATHERTON
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Patent number: 11373968Abstract: A semiconductor die may be coupled to a printed circuit board using a solder ball. The semiconductor die comprises a redistribution layer formed above a semiconductor chip, a polymer layer formed on the redistribution layer, and an Under Bump Metallurgy (UBM) layer formed on the polymer layer. The polymer layer comprises a plurality of vias, which electrically couple the UBM layer to the redistribution layer. The entire UBM layer may be deposited with a continuously flat upper surface for coupling to the solder ball. The plurality of vias may be positioned such that they are centered on a point that is not central to the UBM layer.Type: GrantFiled: April 24, 2020Date of Patent: June 28, 2022Assignee: Cirrus Logic, Inc.Inventors: Yaoyu Pang, Steven A. Atherton
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Patent number: 11322465Abstract: A method may include forming a metal pattern in a metal layer of a fabricated integrated circuit device and under a target bump of the fabricated integrated circuit device, wherein the metal pattern has an inner shape and an outer field such that a void space in the metal layer is created between the inner shape and the outer field and approximately centering the void space on an outline of an under-bump metal formed under the target bump with a keepout distance from the inner shape and the outer field on either side of the outline such that the metal minimizes local variations in mechanical stress on underlying structures within the fabricated integrated circuit device.Type: GrantFiled: June 9, 2020Date of Patent: May 3, 2022Assignee: Cirrus Logic, Inc.Inventors: Kathryn R. Holland, Marc L. Tarabbia, Yaoyu Pang, Alexander Barr
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Publication number: 20210066221Abstract: A method may include forming a metal pattern in a metal layer of a fabricated integrated circuit device and under a target bump of the fabricated integrated circuit device, wherein the metal pattern has an inner shape and an outer field such that a void space in the metal layer is created between the inner shape and the outer field and approximately centering the void space on an outline of an under-bump metal formed under the target bump with a keepout distance from the inner shape and the outer field on either side of the outline such that the metal minimizes local variations in mechanical stress on underlying structures within the fabricated integrated circuit device.Type: ApplicationFiled: June 9, 2020Publication date: March 4, 2021Applicant: Cirrus Logic International Semiconductor Ltd.Inventors: Kathryn Rose HOLLAND, Marc L. TARABBIA, Yaoyu PANG, Alexander BARR
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Publication number: 20200343206Abstract: A semiconductor die may be coupled to a printed circuit board using a solder ball. The semiconductor die comprises a redistribution layer formed above a semiconductor chip, a polymer layer formed on the redistribution layer, and an Under Bump Metallurgy (UBM) layer formed on the polymer layer. The polymer layer comprises a plurality of vias, which electrically couple the UBM layer to the redistribution layer. The entire UBM layer may be deposited with a continuously flat upper surface for coupling to the solder ball. The plurality of vias may be positioned such that they are centered on a point that is not central to the UBM layer.Type: ApplicationFiled: April 24, 2020Publication date: October 29, 2020Applicant: Cirrus Logic International Semiconductor Ltd.Inventors: Yaoyu PANG, Steven A. ATHERTON
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Patent number: 10468318Abstract: In one embodiment, an apparatus includes a microelectronic package comprising a plurality of semiconductor chips connected to a substrate and a stiffener mounted on the substrate. The stiffener is mounted on the substrate with the semiconductor chips disposed within an opening in the stiffener and the opening defines an asymmetric shape relative to the semiconductor chips to control overall warpage in the microelectronic package by the stiffener.Type: GrantFiled: January 29, 2018Date of Patent: November 5, 2019Assignee: CISCO TECHNOLOGY, INC.Inventors: Mudasir Ahmad, Weidong Xie, Qiang Wang, Yaoyu Pang
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Publication number: 20190237371Abstract: In one embodiment, an apparatus includes a microelectronic package comprising a plurality of semiconductor chips connected to a substrate and a stiffener mounted on the substrate. The stiffener is mounted on the substrate with the semiconductor chips disposed within an opening in the stiffener and the opening defines an asymmetric shape relative to the semiconductor chips to control overall warpage in the microelectronic package by the stiffener.Type: ApplicationFiled: January 29, 2018Publication date: August 1, 2019Applicant: CISCO TECHNOLOGY, INC.Inventors: Mudasir Ahmad, Weidong Xie, Qiang Wang, Yaoyu Pang
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Publication number: 20190207363Abstract: Systems, devices, methods, and computer-readable media for preventing laser kink failures. A laser diode device can include one or more laser diodes configured to emit electromagnetic radiation coherently. The laser diode device can also include one or more submounts upon which the one or more laser diodes are mounted. The one or more submounts can include one or more through vias including one or more fill materials different from a material of the one or more submounts. Further, one or more properties of the one or more through vias in the one or more submounts can be selected to reduce an amount of mismatch between an effective coefficient of thermal expansion of the one or more laser diodes and an effective coefficient of thermal expansion of the one or more submounts.Type: ApplicationFiled: March 8, 2019Publication date: July 4, 2019Inventors: Mudasir Ahmad, Weidong Xie, Yaoyu Pang, Chiyu Liu, Qiang Wang
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Patent number: 10230212Abstract: Systems, devices, methods, and computer-readable media for preventing laser kink failures. A laser diode device can include one or more laser diodes configured to emit electromagnetic radiation coherently. The laser diode device can also include one or more submounts upon which the one or more laser diodes are mounted. The one or more submounts can include one or more through vias including one or more fill materials different from a material of the one or more submounts. Further, one or more properties of the one or more through vias in the one or more submounts can be selected to reduce an amount of mismatch between an effective coefficient of thermal expansion of the one or more laser diodes and an effective coefficient of thermal expansion of the one or more submounts.Type: GrantFiled: December 22, 2017Date of Patent: March 12, 2019Assignee: Cisco Technology, Inc.Inventors: Mudasir Ahmad, Weidong Xie, Yaoyu Pang, Chiyu Liu, Qiang Wang
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Patent number: 9281269Abstract: An integrated circuit (IC) package, device, including a substrate having a top surface with an IC die mounting area and a peripheral area surrounding the mounting area, a plurality of parallel conductor layers, a plurality of insulating layers and a plurality of plated through holes (PTHs) extending through the conductor layers and insulating layers. Various substrate structures in which certain of the PTHs and/or conductor layers and/or insulating layers have different CTE's than the others is disclosed. The various structures may reduce circuit failures due to substrate warpage and/or solder joint damage associated with a CTE mismatch between the substrate and the IC die.Type: GrantFiled: November 20, 2012Date of Patent: March 8, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Jaimal Mallory Williamson, Nima Shahidi, Yaoyu Pang
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Publication number: 20140138822Abstract: An integrated circuit (IC) package, device, including a substrate having a top surface with an IC die mounting area and a peripheral area surrounding the mounting area, a plurality of parallel conductor layers, a plurality of insulating layers and a plurality of plated through holes (PTHs) extending through the conductor layers and insulating layers. Various substrate structures in which certain of the PTHs and/or conductor layers and/or insulating layers have different CTE's than the others is disclosed. The various structures may reduce circuit failures due to substrate warpage and/or solder joint damage associated with a CTE mismatch between the substrate and the IC die.Type: ApplicationFiled: November 20, 2012Publication date: May 22, 2014Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Jaimal Mallory Williamson, Nima Shahidi, Yaoyu Pang