Abstract: The present application discloses an MV device, wherein a first gate structure of the MV device is formed by stacking a first gate dielectric layer and a first gate conductive material layer. The first gate dielectric layer is divided into a body gate dielectric layer and an edge gate dielectric layer. The body gate dielectric layer is located in a middle region, and the edge gate dielectric layer surrounds the periphery of the body gate dielectric layer. A channel region is located in a surface of the semiconductor substrate between the lightly doped drain regions on the two sides of the first gate structure. In a channel length direction, the top of the channel region is covered by the body gate dielectric layer. The present application also discloses a method for manufacturing the MV device.

Abstract: The present application provides a process method for improving reliability of a metal gate high-voltage device. Stacks layers formed over the gate oxide layer and spaced apart from each other. An SiCN layer is deposited to cover tops and sidewalls of the stack layers, and cover bottoms of slots between the stack layers. An HARP layer is deposited to covert the SiCN layer. The HARP layer over the stack layers and the slot regions is covered with a photoresist. Photolithography and etching are sequentially performed to open the HARP layer over the stack layers. The photoresist in the slot regions is reserved. The HARP layer over the stack layers outside the slot regions is removed. The operations are repeated for many times until the slot regions are filled with the HARP layer.