Abstract: The present invention provides a compound of Formula (I), or a solvate, a tautomer, a stereoisomer or a salt thereof, for use in the treatment of cancer, in particular prostate cancer. These compounds are of use in cancer immunotherapy and may be used in combination therapies with immune checkpoint inhibitors and tumour microenvironment modulators. The invention also provides compositions comprising the compounds of the invention, as well as the use of compounds of the invention as STAT3 inhibitors.

Abstract: A method and device for identifying leaks in or a leakage rate of an integrated circuit package. The method and device include integrating a micromachined-thermal-convection accelerometer in the integrated circuit package and evaluating the initial and subsequent sensitivities of the accelerometer. A change in sensitivity with time provides indicia of a leak and a measure of leakage rate.

Abstract: A method and device for identifying leaks in or a leakage rate of an integrated circuit package. The method and device include integrating a micromachined-thermal-convection accelerometer in the integrated circuit package and evaluating the initial and subsequent sensitivities of the accelerometer. A change in sensitivity with time provides indicia of a leak and a measure of leakage rate.

Abstract: A wafer-level packaged IC is made by attaching a cap wafer to the front of an IC base wafer before cutting the IC base wafer, i.e. before singulating the plurality of dies on the IC base wafer. The cap wafer is mechanically attached and electrically connected to the IC base wafer, then the dies are singulated. Electrically conductive paths extend through the cap wafer, between wafer contact pads on the front surface of the cap and electrical contact points on the IC base wafer. Optionally, the cap wafer contains one or more dies. The IC base wafer can be fabricated according to a different technology than the cap wafer, thereby forming a hybrid wafer-level package. Optionally, additional “upper-level” cap wafers (with or without dies) can be stacked to form a “multi-story” IC. Optionally, a hermetically-sealed cavity headroom is provided.

Abstract: Single chip 3-axis thermal accelerometer devices include a substrate, at least one cavity etched in the substrate, a fluid disposed in the cavity, a bridge structure suspended over an opening of the cavity, and a plurality of heater elements and temperature sensing elements disposed on the bridge structure. The substrate has a substantially planar surface defined by X and Y coordinate axes, and the bridge structure is suspended over the opening of the cavity in the X-Y plane. In one embodiment, the bridge structure is configured to position at least two of the temperature sensing elements out of the X-Y plane. The heater and temperature sensing elements are disposed on the bridge structure in optimized arrangements for providing reduced temperature coefficients and for producing output voltages having reduced DC offset and drift.

Abstract: Single chip 3-axis thermal accelerometer devices include a substrate, at least one cavity etched in the substrate, a fluid disposed in the cavity, a bridge structure suspended over an opening of the cavity, and a plurality of heater elements and temperature sensing elements disposed on the bridge structure. The substrate has a substantially planar surface defined by X and Y coordinate axes, and the bridge structure is suspended over the opening of the cavity in the X-Y plane. In one embodiment, the bridge structure is configured to position at least two of the temperature sensing elements out of the X-Y plane. The heater and temperature sensing elements are disposed on the bridge structure in optimized arrangements for providing reduced temperature coefficients and for producing output voltages having reduced DC offset and drift.

Abstract: A wafer-level packaged IC is made by attaching a cap wafer to the front of an IC base wafer before cutting the IC base wafer, i.e. before singulating the plurality of dies on the IC base wafer. The cap wafer is mechanically attached and electrically connected to the IC base wafer, then the dies are singulated. Electrically conductive paths extend through the cap wafer, between wafer contact pads on the front surface of the cap and electrical contact points on the IC base wafer. Optionally, the cap wafer contains one or more dies. The IC base wafer can be fabricated according to a different technology than the cap wafer, thereby forming a hybrid wafer-level package. Optionally, additional “upper-level” cap wafers (with or without dies) can be stacked to form a “multi-story” IC. Optionally, a hermetically-sealed cavity headroom is provided.

Abstract: A method of etching a trench in a substrate using a dry plasma etch technique that allows precise control of lateral undercut. The method includes optionally forming at least one on-chip device or micro-machined structure in a surface of a silicon substrate, and covering the surface with a masking layer. A trench pattern is then imaged in or transferred to the masking layer for subsequent etching of the substrate. Upper portions of the trench are anisotropically etched in the substrate. The trench is then semi-anisotropically etched and isotropically etched in the substrate. By modifying isotropic etching time, a controlled lateral undercut can be achieved as the trench is etched vertically in the substrate.

Abstract: A method of etching a trench in a substrate using a dry plasma etch technique that allows precise control of lateral undercut. The method includes optionally forming at least one on-chip device or micro-machined structure in a surface of a silicon substrate, and covering the surface with a masking layer. A trench pattern is then imaged in or transferred to the masking layer for subsequent etching of the substrate. Upper portions of the trench are anisotropically etched in the substrate. The trench is then semi-anisotropically etched and isotropically etched in the substrate. By modifying isotropic etching time, a controlled lateral undercut can be achieved as the trench is etched vertically in the substrate.