Abstract: A disclosed gateway system comprises a classification component configured to classify a stream of data packets received by the gateway system into a plurality of groups, each of the groups associated with a respective communication port of a payload system, and a frame constructor configured to construct for each of the groups of classified data packets payload-frames comprising data of the classified data packets and target information indicative of at least the respective communication port associated with the classified data packets. The classification component can be configured to classify the received stream of data packets based on destination tags embedded in said the packets.

Abstract: A network device includes a first port configured to receive an incoming data packet. A memory stores the incoming data packet. A second port is configured to transmit outgoing packets. A packet processor is configured to generate a data structure, corresponding to the incoming data packet, that includes information based on a header portion of the incoming data packet and, in each of a plurality of processing operations, perform at least one processing task on the data packet using the data structure. The processing operations include adding to and/or subtracting from the information stored in the data structure, and preparing the data structure to be further modified in a subsequent processing operation. The packet processor is further configured to modify the header portion according to the data structure as modified at the plurality of processing operations and provide the stored data packet with the modified header portion to the second port.

Abstract: A packet processor for a network device includes an incoming port that receives a first packet. The first packet includes a data portion, a control portion and a first outgoing port. A control data processing device receives the control portion from the incoming port while the data portion is stored in memory, and transmits the control portion to the first outgoing port. The first outgoing port transmits a first request for the data portion based on the control portion. A header altering device retrieves the data portion from the memory and strips, modifies, and encapsulates the data portion based on the first request.

Abstract: A network device includes memory having memory banks, and a packet processor module configured to receive bursts of packets and segment a received packet into a plurality of sections corresponding to the memory banks. The memory is configured to store a first section of a first received packet at a first one of the memory banks, continue storing remaining sections of the first received packet in remaining ones of the memory banks, and begin storing sections of a second received packet at a second one of the memory banks. The second one of the memory banks is offset from the first one of the memory banks by at least one of a number of memory banks that is less than a total number of memory banks required to store the first received packet, and a number of banks that is randomly selected for each of the packets.

Abstract: A packet processor for a network device includes an incoming port that receives a first packet. The first packet includes a data portion, a control portion and a first outgoing port. A control data processing device receives the control portion from the incoming port while the data portion is stored in memory, and transmits the control portion to the first outgoing port. The first outgoing port transmits a first request for the data portion based on the control portion. A header altering device retrieves the data portion from the memory and strips, modifies, and encapsulates the data portion based on the first request.

Abstract: In a data transfer interface, at least one deserializer receives a serial data stream at a first clock speed and outputs a first parallel data stream at a second clock speed. The first parallel data stream includes data symbols representing data and alignment symbols for aligning the data symbols at a downstream location. A demultiplexer demultiplexes the first parallel data stream into a plurality of second parallel data streams based on the alignment symbols.

Abstract: A network storage system includes an address adjusting module that includes a segmented packet receiver module that receives M sections of a segmented packet, where M is an integer greater than one. A bank identification (ID) overwriter module overwrites a bank ID of at least one of the M sections of the packet with a control bank ID that is different than the bank ID.

Abstract: A packet processor for a switch/router alters headers of packets and includes a plurality of ports Memory buffers a first portion of a first packet that is received by an incoming port. A control data processor receives a first control portion of the first packet from the incoming port and transmits the first control portion to one or more outgoing ports. A header altering device strips, modifies and encapsulates the first portion on egress from the packet processor based upon one or more protocol layering requirements of the one or more outgoing ports. The protocol layering requirements include bridged or tunneled Ethernet, unicast or multicast multi-protocol label switching (MPLS), and IPv4 and IPv6 routed.