Patents by Inventor Yaron Alankry

Yaron Alankry has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9813242
    Abstract: An integrated circuit (IC) package includes a storage element and a protection component coupled to the storage element. The protection component includes a breach detection component configured to detect an attempted breach of the IC package. The protection component further includes a time detection component configured to determine a breach timestamp associated with a time of occurrence of the attempted breach and configured to store a representation of the breach timestamp in the storage element. The storage element may be configured to store a sensitive datum, and the time detection component may be configured to store the representation of the breach timestamp by overwriting the sensitive datum in the storage element with the representation of the breach timestamp.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: November 7, 2017
    Assignee: NXP USA, Inc.
    Inventors: Ron-Michael Bar, Yaron Alankry, Eran Glickman
  • Publication number: 20160380769
    Abstract: An integrated circuit (IC) package includes a storage element and a protection component coupled to the storage element. The protection component includes a breach detection component configured to detect an attempted breach of the IC package. The protection component further includes a time detection component configured to determine a breach timestamp associated with a time of occurrence of the attempted breach and configured to store a representation of the breach timestamp in the storage element. The storage element may be configured to store a sensitive datum, and the time detection component may be configured to store the representation of the breach timestamp by overwriting the sensitive datum in the storage element with the representation of the breach timestamp.
    Type: Application
    Filed: June 25, 2015
    Publication date: December 29, 2016
    Inventors: Ron-Michael Bar, Yaron Alankry, Eran Glickman
  • Patent number: 8458364
    Abstract: A device having frame receiving and processing capabilities and a method for receiving and processing frames. The method includes: receiving a frame; associating a frame timestamp with the frame; storing the frame and the associated timestamp at a certain buffer out of a group of buffers; generating a valid timing information frame indicator if the received frame is a valid timing information frame; and storing the valid timing information frame indicator at a certain buffer descriptor associated with the certain buffer.
    Type: Grant
    Filed: August 2, 2006
    Date of Patent: June 4, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Yaron Alankry, Eran Glickman, Erez Parnes, Daniel Rozovsky
  • Patent number: 8452553
    Abstract: A device and a method. The device includes: (i) a processor, connected to the receiver, (ii) an interface adapted to receive a test vector and to output a test response, the test vector includes a first group of signals that include idle signals and at least one information frame and a second group of signals that include timing signals and data signals; and (iii) a receiver, connected to the interface. The receiver is adapted to receive the first group of signals and filter out the idle signals and at least one instruction frame delimiters to provide at least one instruction. The device is adapted to send the at least one instruction to at least one instruction buffer. The processor is adapted to execute at least one instruction stored in the at least one instruction buffer and to respond to the second group of signals such as to provide test responses.
    Type: Grant
    Filed: November 30, 2006
    Date of Patent: May 28, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Eran Glickman, Yaron Alankry, Erez Arbel-Meirovich, Erez Parnes
  • Patent number: 8089978
    Abstract: A device having under-run management capabilities and to a method for managing under-runs. The method includes providing, to a memory unit, channel information from multiple channels; allocating time slots for communication channel transmissions; the method is characterized by including: sending, during a time slot allocated for a transmission of channel information from an enabled communication channel, to the shift register channel information of an enabled communication channel, serially outputting the received channel information from the shift register towards a communication line while serially replacing the outputted channel information by a predefined content such that the shift register stores a communication channel disable code when an under-run occurs; defining a communication channel as a disabled communication channel once the under-run occurs; and transmitting, during a time slot allocated to a disabled communication channel, idle signals to the communication line.
    Type: Grant
    Filed: November 9, 2005
    Date of Patent: January 3, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Eran Glickman, Yaron Alankry, Adi Katz
  • Patent number: 7886090
    Abstract: A method for managing under-runs and a device having under-run management capabilities. The method includes retrieving packets from multiple buffers, monitoring a state of a multiple buffers, determining whether an under-run associated with a transmission attempt of a certain information frame from a certain buffer occurs; if an under-run occurs, requesting a certain information frame transmitter to transmit predefined packets while ignoring packets that are retrieved from the certain buffer, until a last packet of the information frame is retrieved from the certain buffer; and notifying a processor that an under-run occurred after at least one predefined packet was transmitted; wherein each buffer out of the multiple buffers is adapted to store a fraction of a maximal sized information frame.
    Type: Grant
    Filed: January 4, 2006
    Date of Patent: February 8, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Yaron Alankry, Eran Glickman, Erez Parnes
  • Patent number: 7787484
    Abstract: A method that includes defining a transmission schedule of a TDM data frame that includes multiple TDM time slots allocated for transmitting data over a TDM line; the method is characterized by including: providing a transmission clock signal having a transmission clock frequency to the TDM line, providing a first clock signal having a first clock frequency to data sources that belong to a first group of data sources and providing a second clock signal having a second clock frequency to data sources that belong to a second group of data sources; wherein the first clock frequency and the second clock frequency are higher than the transmission clock frequency; pre-fetching, to a first intermediate storage a data segment from a data source out of the first group of data sources in response to a fullness level of the first intermediate storage unit and to the transmission schedule; pre-fetching, to a second intermediate storage a data segment from a data source out of the second group of data sources in response
    Type: Grant
    Filed: May 29, 2006
    Date of Patent: August 31, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Eran Glickman, Yaron Alankry, Erez Parnes
  • Publication number: 20100114508
    Abstract: A device and a method. The device includes: (i) a processor, connected to the receiver, (ii) an interface adapted to receive a test vector and to output a test response, the test vector includes a first group of signals that include idle signals and at least one information frame and a second group of signals that include timing signals and data signals; and (iii) a receiver, connected to the interface. The receiver is adapted to receive the first group of signals and filter out the idle signals and at least one instruction frame delimiters to provide at least one instruction. The device is adapted to send the at least one instruction to at least one instruction buffer. The processor is adapted to execute at least one instruction stored in the at least one instruction buffer and to respond to the second group of signals such as to provide test responses.
    Type: Application
    Filed: November 30, 2006
    Publication date: May 6, 2010
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Eran Glickman, Yaron Alankry, Erez Arbel-Meirovich, Erez Parnes
  • Publication number: 20090310726
    Abstract: A device having frame receiving and processing capabilities and a method for receiving and processing frames. The method includes: receiving a frame; associating a frame timestamp with the frame; storing the frame and the associated timestamp at a certain buffer out of a group of buffers; generating a valid timing information frame indicator if the received frame is a valid timing information frame; and storing the valid timing information frame indicator at a certain buffer descriptor associated with the certain buffer.
    Type: Application
    Filed: August 2, 2006
    Publication date: December 17, 2009
    Applicant: Freescale Semiconductor, Inc
    Inventors: Yaron Alankry, Eran Glickman, Erez Parnes, Daniel Rozovsky
  • Publication number: 20090303872
    Abstract: A device having under-run management capabilities and to a method for managing under-runs. The method includes providing, to a memory unit, channel information from multiple channels; allocating time slots for communication channel transmissions; the method is characterized by including: sending, during a time slot allocated for a transmission of channel information from an enabled communication channel, to the shift register channel information of an enabled communication channel, serially outputting the received channel information from the shift register towards a communication line while serially replacing the outputted channel information by a predefined content such that the shift register stores a communication channel disable code when an under-run occurs; defining a communication channel as a disabled communication channel once the under-run occurs; and transmitting, during a time slot allocated to a disabled communication channel, idle signals to the communication line.
    Type: Application
    Filed: November 9, 2005
    Publication date: December 10, 2009
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Eran Glickman, Yaron Alankry, Adi Katz
  • Publication number: 20090274168
    Abstract: A method that includes defining a transmission schedule of a TDM data frame that includes multiple TDM time slots allocated for transmitting data over a TDM line; the method is characterized by including: providing a transmission clock signal having a transmission clock frequency to the TDM line, providing a first clock signal having a first clock frequency to data sources that belong to a first group of data sources and providing a second clock signal having a second clock frequency to data sources that belong to a second group of data sources; wherein the first clock frequency and the second clock frequency are higher than the transmission clock frequency; pre-fetching, to a first intermediate storage a data segment from a data source out of the first group of data sources in response to a fullness level of the first intermediate storage unit and to the transmission schedule; pre-fetching, to a second intermediate storage a data segment from a data source out of the second group of data sources in response
    Type: Application
    Filed: May 29, 2006
    Publication date: November 5, 2009
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Eran Glickman, Yaron Alankry, Erez Parnes
  • Publication number: 20090198926
    Abstract: A method, the method includes providing data; retrieving interleaving command information from a two dimensional array of interleaving command information; wherein the two dimensional array includes multiple interleaving command information rows, each row includes interleaving commands associated with multiple TDM time slots; and determining, in response to the retrieved interleaving command information, whether to provide data from a first data source or from a second data source.
    Type: Application
    Filed: May 29, 2006
    Publication date: August 6, 2009
    Applicant: CITIBANK, N.A.
    Inventors: Eran Glickman, Yaron Alankry, Avihai Graizei
  • Publication number: 20080307127
    Abstract: A method for managing under-runs and a device having under-run management capabilities. The method includes retrieving packets from multiple buffers, monitoring a state of a multiple buffers, determining whether an under-run associated with a transmission attempt of a certain information frame from a certain buffer occurs; if an under-run occurs, requesting a certain information frame transmitter to transmit predefined packets while ignoring packets that are retrieved from the certain buffer, until a last packet of the information frame is retrieved from the certain buffer; and notifying a processor that an under-run occurred after at least one predefined packet was transmitted; wherein each buffer out of the multiple buffers is adapted to store a fraction of a maximal sized information frame.
    Type: Application
    Filed: January 4, 2006
    Publication date: December 11, 2008
    Inventors: Yaron Alankry, Eran Glickman, Erez Parnes