Abstract: A distributed interconnect bus apparatus for connecting peripheral devices. The apparatus can be utilized to wirelessly connect peripheral devices or to allow the connectivity of such devices over a network. The apparatus includes a first bridge coupled to a root component of an interconnect bus; and a second bridge coupled to an endpoint component of an interconnect bus. The apparatus may further include an acknowledgment (ACK) termination for generating at least an ACK signal; and a flow control mechanism including at least one receiver buffer for temporarily saving data packets of multiple different transactions.

Abstract: A wireless communication system comprises a root component connected in a host device and directly coupled to an upstream bus unit, wherein the upstream bus unit is configured to maintain a first configuration space and a copy of a second configuration space, the first configuration space bridge includes at least hot-plug registers specifying at least capabilities and status of a slot of the upstream bus unit; and at least one endpoint component connected to at least one peripheral device and directly coupled to a downstream bus unit that communicates with the host bridge over a distributed link established over a distributed peripheral component interconnect express (PCIe) bus, wherein the downstream bus unit is configured to maintain the second configuration space; the second configuration space includes at least hot-plug registers specifying at least capabilities and status of a slot of the downstream bus unit.

Abstract: A distributed PCIe adapted to support a hot-plug process triggered by any change in a status of a distributed link, comprises an upstream bus unit including a first bridge connected to a root component and adapted to maintain a first configuration space and a copy of a second configuration space, the first configuration space bridge includes at least hot-plug registers specifying at least capabilities and status of a slot of the first bridge; and a second bridge connected to an endpoint component and adapted to maintain the second configuration space, the second configuration space includes at least hot-plug registers specifying at least capabilities and status of a slot of the second bridge.

Abstract: A distributed PCIe adapted to support a hot-plug process triggered by any change in a status of a distributed link, comprises an upstream bus unit including a first bridge connected to a root component and adapted to maintain a first configuration space and a copy of a second configuration space, the first configuration space bridge includes at least hot-plug registers specifying at least capabilities and status of a slot of the first bridge; and a second bridge connected to an endpoint component and adapted to maintain the second configuration space, the second configuration space includes at least hot-plug registers specifying at least capabilities and status of a slot of the second bridge.

Abstract: A distributed interconnect bus apparatus for connecting peripheral devices. The apparatus can be utilized to wirelessly connect peripheral devices or to allow the connectivity of such devices over a network. The apparatus includes a first bridge coupled to a root component of an interconnect bus; and a second bridge coupled to an endpoint component of an interconnect bus. The apparatus may further include an acknowledgment (ACK) termination for generating at least an ACK signal; and a flow control mechanism including at least one receiver buffer for temporarily saving data packets of multiple different transactions.

Abstract: A first serial buffer having a delivering end may deliver first data from a first position. A second serial buffer having a delivering end may deliver second data from a second position. The first position relative to the delivering end of the first serial buffer may be different than the second position relative to the delivering end of the second serial buffer.

Abstract: Various embodiments in the invention relate to storing information in a memory to load a plurality of configuration registers of an electronic device, where the information includes a plurality of configuration register data and corresponding configuration register address information. Thus, the configuration register data may be loaded to various configuration registers selected according to the configuration register address information. Moreover, during testing it is possible to identify configuration registers which reset to a default data value equal to desired data for achieving a desired device configuration prior to being loaded. Then, the configuration register data and address information for loading those identified registers can be removed from the memory, and the memory size can be reduced by a size necessary to hold the removed configuration register data and address information.

Abstract: A first serial buffer having a delivering end may deliver first data from a first position. A second serial buffer having a delivering end may deliver second data from a second position. The first position relative to the delivering end of the first serial buffer may be different than the second position relative to the delivering end of the second serial buffer.

Abstract: Briefly, a re-timing buffer system that may insert or remove dummy data during frequency translation.

Abstract: A method system and apparatus for implementing clock delay insertion for modules of chips using programmable clock delay units are described. The system for adding a clock delay to the clock input of a module includes a module and a programmable clock delay unit pre-pended to the module and configured to add a programmed clock delay.