Patents by Inventor Yaron KITTNER
Yaron KITTNER has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230393971Abstract: A system for distributed storage agents includes at least one memory and at least one compute node comprising at least one agent module. The at least one agent module is configured to cause at least a portion of data stored in the at least one memory to be pushed to a destination in accordance with an agent access plan.Type: ApplicationFiled: August 17, 2023Publication date: December 7, 2023Applicant: NeuroBlade Ltd.Inventors: Yoav MARKUS, Eliad HILLEL, Ilan MAYER-WOLF, Yaron KITTNER
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Patent number: 11706144Abstract: A network device includes a rate measurement circuit that is configured to measure respective egress rates at which respective data is being transmitted via respective ports associated with the network device. A marking ratio determination circuit is configured to select respective marking ratios based on respective measured egress rates, the marking ratios for marking packets to be transmitted via the respective ports to indicate respective levels of congestion corresponding to the respective ports. Different marking ratios correspond to different measured egress rates. A packet editor circuit is configured to mark selected packets to be transmitted via respective ports according to the respective selected marking ratios. The respective selected marking ratios indicate to other communication devices that respective network paths via which the selected packets travelled experienced congestion, and the respective marking ratios indicate respective levels of congestion.Type: GrantFiled: May 6, 2021Date of Patent: July 18, 2023Assignee: Marvell Israel (M.I.S.L) Ltd.Inventors: Gideon Navon, Rami Zemach, Yaron Kittner
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Publication number: 20230222108Abstract: Disclosed embodiments include system including a hardware based, programmable data analytics processor configured to reside between a data storage unit and one or more hosts. The programmable data analytics processor includes a selector module configured to input a first set of data and, based on a selection indicator, output a first subset of the first set of data; a filter and project module configured to input a second set of data and, based on a function, output an updated second set of data; a join and group module configured to combine data from one or more third data sets into a combined data set; and a communications fabric configured to transfer data between any of the selector module, the filter and project module, and the join and group module.Type: ApplicationFiled: March 15, 2023Publication date: July 13, 2023Applicant: NEUROBLADE LTD.Inventors: Eliad HILLEL, Elad SITY, Gal DAYAN, Ilan MAYER-WOLF, Yoav MARKUS, Yaron KITTNER, Oded TRAININ, Gal HAI
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Publication number: 20230222126Abstract: Disclosed embodiments include a data filter system including an interface and data filter circuitry. The data filter circuitry is configured to receive a data filter initiation signal via the interface, and in response to receipt of the data filter initiation signal, perform at least one operation associated with a data query, wherein the data query implicates a body of data stored in at least one storage unit; wherein performance of the at least one operation associated with the data query results in generation of a filtered data subset from the body of data, including less data than the body of data implicated by the data query; and transfer the filtered data subset to a host processor configured to perform one or more additional operations relative to the data query to generate an output to the data query.Type: ApplicationFiled: March 15, 2023Publication date: July 13, 2023Applicant: NEUROBLADE LTD.Inventors: Yaron KITTNER, Gal HAI
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Patent number: 11689440Abstract: A network device comprises a network interface configured to transmit packets via a network link, and timestamp circuitry configured to modify a packet that is to be transmitted by the network interface circuitry by embedding a future timestamp in the packet. The future timestamp corresponds to a transmit time at which the packet is to be transmitted by the network interface circuitry, and the transmit time occurs after the timestamp circuitry embeds the timestamp in the packet. Time gating circuitry is configured to i) receive the packet, ii) determine when a current time indicated by a clock circuit reaches the transmit time, iii) hold the packet from proceeding to the network interface circuitry prior to the current time reaching the transmit time, and iv) release the packet in response to the current time reaching the transmit time.Type: GrantFiled: November 21, 2019Date of Patent: June 27, 2023Assignee: Marvell Israel (M.I.S.L) Ltd.Inventors: Rami Zemach, Yaron Kittner, Nitzan Dror
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Publication number: 20230072376Abstract: A network device includes a first queue for queueing express packets and a second queue for queueing preemptable packets that are to be transmitted via a network interface of the network device. The network device also includes a transmit controller that receives a packet directed to the first queue and determines whether the packet is a type of packet that requires transmission at a specific transmit time from the network interface of the network device. In response to determining that the packet is a type of packet that requires transmission at a specific transmit time, the transmit controller suspends an ongoing transmission of a preemptable packet from the second queue that would prevent transmission of the packet from the first queue at the specific transmit time via the network interface and causes the packet in the first queue to be transmitted at the specific transmit time via the network interface.Type: ApplicationFiled: August 31, 2022Publication date: March 9, 2023Inventors: Yaron Kittner, Joergen P.R. Hofman-Bang, Rami ZEMACH, Nitzan DROR
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Publication number: 20230052252Abstract: A network device provides a search key corresponding to a packet to a TCAM. The TCAM determines that the search key matches one or more search patterns stored in the TCAM. The network device selects one search pattern among the one or more search patterns at least by analyzing respective priority information associated with the one or more search patterns. The respective priority information indicates one or more respective priority levels that are independent from one or more physical locations of the one or more search patterns within the TCAM. In connection with selecting the one search pattern, the network device determines one or more actions to be performed on the packet by the network device, the one or more actions corresponding to the selected one search pattern.Type: ApplicationFiled: August 11, 2022Publication date: February 16, 2023Inventors: Yaron KATZRI, Yaron KITTNER
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Publication number: 20220321588Abstract: An anomaly detection apparatus for detecting anomalies in network traffic includes a statistics generator that receives characteristics of packets in network traffic and to generate statistics for the network traffic. The statistics include distribution statistics regarding respective distributions of respective characteristics of packets in the network traffic over time. An anomaly detection processor detects deviations in the distribution statistics as compared to distribution statistics for normal network traffic and detects anomalies regarding the network traffic based on the deviations in the distribution statistics as compared to distribution statistics for the normal network traffic.Type: ApplicationFiled: April 5, 2022Publication date: October 6, 2022Inventors: Gideon Navon, Ziv Tomarov, Yaron Kittner
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Patent number: 11405327Abstract: A network device includes a transmit buffer from which data is transmitted to a network, and a packet buffer from which data chunks are transmitted to the transmit buffer in response to read requests. The packet buffer has a maximum read latency from receipt of a read request to transmission of a responsive data chunk, and receives read requests including a read request for a first data chunk of a network packet and a plurality of additional read requests for additional data chunks of the network packet. A latency timer monitors elapsed time from receipt of the first read request, and outputs a latency signal when the elapsed time reaches the first maximum read latency. Transmission logic waits until the elapsed time equals the first maximum read latency, and then transmits the first data chunk from the transmit buffer, without regard to a fill level of the transmit buffer.Type: GrantFiled: October 14, 2020Date of Patent: August 2, 2022Assignee: Marvell Israel (M.I.S.L) Ltd.Inventors: Rami Zemach, Yaron Kittner
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Patent number: 11329923Abstract: A network device for a communications network includes a port configured to transmit data to the network at a maximum transmit data rate. The device also includes a transmit buffer configured to buffer data units that are ready for transmission to the network, and a packet buffer configured to buffer data units before the data units are ready for transmission. The packet buffer is configured to output data units at a maximum packet buffer transmission rate faster than the maximum transmit data rate. The device includes a rate controller configured to control a transmission rate of data from the packet buffer to the transmit buffer so that averaged over a period, the transmission rate from the packet buffer to the transmit buffer is at most equal to the maximum transmit data rate, while allowing the transmission rate, at one or more time intervals, to exceed the maximum transmit data rate.Type: GrantFiled: August 4, 2020Date of Patent: May 10, 2022Assignee: Marvell Israel (M.I.S.L) Ltd.Inventors: Rami Zemach, Yaron Kittner
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Publication number: 20210352016Abstract: A network device includes a rate measurement circuit that is configured to measure respective egress rates at which respective data is being transmitted via respective ports associated with the network device. A marking ratio determination circuit is configured to select respective marking ratios based on respective measured egress rates, the marking ratios for marking packets to be transmitted via the respective ports to indicate respective levels of congestion corresponding to the respective ports. Different marking ratios correspond to different measured egress rates. A packet editor circuit is configured to mark selected packets to be transmitted via respective ports according to the respective selected marking ratios. The respective selected marking ratios indicate to other communication devices that respective network paths via which the selected packets travelled experienced congestion, and the respective marking ratios indicate respective levels of congestion.Type: ApplicationFiled: May 6, 2021Publication date: November 11, 2021Inventors: Gideon NAVON, Rami ZEMACH, Yaron KITTNER
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Publication number: 20210185153Abstract: A packet processor of a network device includes a forwarding engine that is configured to determine egress network interfaces via which packets received by the network device are to be transmitted. The packet processor also includes a header parser configured to parse header information in the packets received by the network device. The header parser includes a first parsing circuit that is configured to parse a first portion of a header of a packet and to prompt a programmable second parsing circuit to parse a second portion of the header. The first portion of the header has a header structure known to the first parsing circuit. The programmable second parsing circuit includes configurable circuitry and a memory to store control information that controls operation of the configurable circuitry to parse the second portion of the header.Type: ApplicationFiled: December 11, 2020Publication date: June 17, 2021Inventors: Yaron KITTNER, Ilan YERUSHALMI, Adar PEERY, Aviram AMIR
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Publication number: 20210029054Abstract: A network device includes a transmit buffer from which data is transmitted to a network, and a packet buffer from which data chunks are transmitted to the transmit buffer in response to read requests. The packet buffer has a maximum read latency from receipt of a read request to transmission of a responsive data chunk, and receives read requests including a read request for a first data chunk of a network packet and a plurality of additional read requests for additional data chunks of the network packet. A latency timer monitors elapsed time from receipt of the first read request, and outputs a latency signal when the elapsed time reaches the first maximum read latency. Transmission logic waits until the elapsed time equals the first maximum read latency, and then transmits the first data chunk from the transmit buffer, without regard to a fill level of the transmit buffer.Type: ApplicationFiled: October 14, 2020Publication date: January 28, 2021Inventors: Rami Zemach, Yaron Kittner
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Publication number: 20200366615Abstract: A network device for a communications network includes a port configured to transmit data to the network at a maximum transmit data rate. The device also includes a transmit buffer configured to buffer data units that are ready for transmission to the network, and a packet buffer configured to buffer data units before the data units are ready for transmission. The packet buffer is configured to output data units at a maximum packet buffer transmission rate faster than the maximum transmit data rate. The device includes a rate controller configured to control a transmission rate of data from the packet buffer to the transmit buffer so that averaged over a period, the transmission rate from the packet buffer to the transmit buffer is at most equal to the maximum transmit data rate, while allowing the transmission rate, at one or more time intervals, to exceed the maximum transmit data rate.Type: ApplicationFiled: August 4, 2020Publication date: November 19, 2020Inventors: Rami Zemach, Yaron Kittner
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Patent number: 10819647Abstract: A network device includes a transmit buffer from which data is transmitted to a network, and a packet buffer from which data chunks are transmitted to the transmit buffer in response to read requests. The packet buffer has a maximum read latency from receipt of a read request to transmission of a responsive data chunk, and receives read requests including a read request for a first data chunk of a network packet and a plurality of additional read requests for additional data chunks of the network packet. A latency timer monitors elapsed time from receipt of the first read request, and outputs a latency signal when the elapsed time reaches the first maximum read latency. Transmission logic waits until the elapsed time equals the first maximum read latency, and then transmits the first data chunk from the transmit buffer, without regard to a fill level of the transmit buffer.Type: GrantFiled: December 3, 2018Date of Patent: October 27, 2020Assignee: Marvell Israel (M.I.S.L) Ltd.Inventors: Rami Zemach, Yaron Kittner
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Patent number: 10785159Abstract: A network device for a communications network includes a port configured to transmit data to the network at a maximum transmit data rate. The device also includes a transmit buffer configured to buffer data units that are ready for transmission to the network, and a packet buffer configured to buffer data units before the data units are ready for transmission. The packet buffer is configured to output data units at a maximum packet buffer transmission rate faster than the maximum transmit data rate. The device includes a rate controller configured to control a transmission rate of data from the packet buffer to the transmit buffer so that averaged over a period, the transmission rate from the packet buffer to the transmit buffer is at most equal to the maximum transmit data rate, while allowing the transmission rate, at one or more time intervals, to exceed the maximum transmit data rate.Type: GrantFiled: December 3, 2018Date of Patent: September 22, 2020Assignee: Marvell Israel (M.I.S.L) Ltd.Inventors: Rami Zemach, Yaron Kittner
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Publication number: 20200252320Abstract: A network device comprises a network interface configured to transmit packets via a network link, and timestamp circuitry configured to modify a packet that is to be transmitted by the network interface circuitry by embedding a future timestamp in the packet. The future timestamp corresponds to a transmit time at which the packet is to be transmitted by the network interface circuitry, and the transmit time occurs after the timestamp circuitry embeds the timestamp in the packet. Time gating circuitry is configured to i) receive the packet, ii) determine when a current time indicated by a clock circuit reaches the transmit time, iii) hold the packet from proceeding to the network interface circuitry prior to the current time reaching the transmit time, and iv) release the packet in response to the current time reaching the transmit time.Type: ApplicationFiled: November 21, 2019Publication date: August 6, 2020Inventors: Rami ZEMACH, Yaron KITTNER, Nitzan DROR
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Patent number: 10678718Abstract: A network device includes a transfer buffer having a plurality of memory banks, and a transfer buffer controller configured to perform a first number of write operations to write processed packets into a memory bank of the transfer buffer, monitor occupancy of the transfer buffer, and when occupancy of the transfer buffer is at least equal to a threshold, perform a predetermined number of read operations during each memory cycle, and when occupancy of the transfer buffer is less than the threshold, perform a second number of read operations, greater than the predetermined number, during each memory cycle. The device concurrently performs multiple read operations and multiple write operations in a single cycle using a plurality of ports. The buffer controller distributes data among the memory banks by allocating write addresses to keep memory occupancy substantially uniform among the memory banks, thereby freeing ports to allow performance of read operations.Type: GrantFiled: October 30, 2018Date of Patent: June 9, 2020Assignee: Marvell Israel (M.I.S.L) Ltd.Inventors: Rami Zemach, Yaron Kittner
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Publication number: 20190220425Abstract: A network device includes a transfer buffer having a plurality of memory banks, and a transfer buffer controller configured to perform a first number of write operations to write processed packets into a memory bank of the transfer buffer, monitor occupancy of the transfer buffer, and when occupancy of the transfer buffer is at least equal to a threshold, perform a predetermined number of read operations during each memory cycle, and when occupancy of the transfer buffer is less than the threshold, perform a second number of read operations, greater than the predetermined number, during each memory cycle. The device concurrently performs multiple read operations and multiple write operations in a single cycle using a plurality of ports. The buffer controller distributes data among the memory banks by allocating write addresses to keep memory occupancy substantially uniform among the memory banks, thereby freeing ports to allow performance of read operations.Type: ApplicationFiled: October 30, 2018Publication date: July 18, 2019Inventors: Rami Zemach, Yaron Kittner
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Publication number: 20190173769Abstract: A network device includes a transmit buffer from which data is transmitted to a network, and a packet buffer from which data chunks are transmitted to the transmit buffer in response to read requests. The packet buffer has a maximum read latency from receipt of a read request to transmission of a responsive data chunk, and receives read requests including a read request for a first data chunk of a network packet and a plurality of additional read requests for additional data chunks of the network packet. A latency timer monitors elapsed time from receipt of the first read request, and outputs a latency signal when the elapsed time reaches the first maximum read latency. Transmission logic waits until the elapsed time equals the first maximum read latency, and then transmits the first data chunk from the transmit buffer, without regard to a fill level of the transmit buffer.Type: ApplicationFiled: December 3, 2018Publication date: June 6, 2019Inventors: Rami Zemach, Yaron Kittner