Abstract: An associative processor includes a plurality of arrays of content addressable memory (CAM) cells and a plurality of tags registers in a tags logic block. Different tags registers are associated with different CAM cell arrays at will, to support parallel execution of the same or different arithmetical operations on two or more CAM cell arrays, and to support pipelined arithmetical operations by having two CAM cell arrays share a tags register to transfer data from one CAM cell array to another using appropriate compare and write operations. All the CAM cell arrays share the same mask and pattern registers. Preferably, at least one tags register is located physically between two of the CAM cell arrays.

Abstract: A data processing device includes an associative processor that in turn includes an array of content addressable memory (CAM) cells and a plurality of tags registers. The device also includes a memory for storing the data and a bus for exchanging the data with the associative processor. Data are exchanged in parallel, via one of the CAM cell columns, one column of data at a time.