Patents by Inventor Yaron Shragai

Yaron Shragai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Converting merge buffer system-kill errors to process-kill errors
    Patent number: 7380169
    Abstract: An apparatus includes a buffer that collects store instruction information associated with one or more processes. The collected store instruction information includes data and addresses where the data are to be stored. The apparatus also includes a buffer control that drains the buffer of store instructions associated with a first process before it collects store instructions associated with a second process.
    Type: Grant
    Filed: September 24, 2004
    Date of Patent: May 27, 2008
    Assignee: Intel Corporation
    Inventors: Tryggve Fossum, Yaron Shragai, Ugonna Echeruo, Shubhendu S. Mukherjee
  • Method of handling errors
    Patent number: 7370231
    Abstract: An error handling routine of a processor, executing in response to a first detected unrecoverable error (DUE) of the processor, responding to an indication that a second DUE has occurred by evaluating the effect of the second DUE on the correctness of the error handling routine.
    Type: Grant
    Filed: December 14, 2004
    Date of Patent: May 6, 2008
    Assignee: Intel Corporation
    Inventors: Tryggve Fossum, Yaron Shragai, Shubhendu S. Mukherjee
  • Poisoned error signaling for proactive OS recovery
    Patent number: 7353433
    Abstract: Use of data poisoning techniques may permit proactive operating system recovery without needing to always bringing down the operating system when uncorrectable errors are encountered.
    Type: Grant
    Filed: December 8, 2003
    Date of Patent: April 1, 2008
    Assignee: Intel Corporation
    Inventors: Kushagra Vaid, Suresh Marisetty, Yaron Shragai, Koichi Yamada, Rajendra Kuramkote, Scott Brenden
  • Method of handling errors
    Publication number: 20060156153
    Abstract: An error handling routine of a processor, executing in response to a first detected unrecoverable error (DUE) of the processor, responding to an indication that a second DUE has occurred by evaluating the effect of the second DUE on the correctness of the error handling routine.
    Type: Application
    Filed: December 14, 2004
    Publication date: July 13, 2006
    Inventors: Tryggve Fossum, Yaron Shragai, Shubhendu Mukherjee
  • Converting merge buffer system-kill errors to process-kill errors
    Publication number: 20060075301
    Abstract: An apparatus includes a buffer that collects store instruction information associated with one or more processes. The collected store instruction information includes data and addresses where the data are to be stored. The apparatus also includes a buffer control that drains the buffer of store instructions associated with a first process before it collects store instructions associated with a second process.
    Type: Application
    Filed: September 24, 2004
    Publication date: April 6, 2006
    Inventors: Tryggve Fossum, Yaron Shragai, Ugonna Echeruo, Shubhendu Mukherjee
  • Poisoned error signaling for proactive OS recovery
    Publication number: 20050138487
    Abstract: Use of data poisoning techniques may permit proactive operating system recovery without needing to always bringing down the operating system when uncorrectable errors are encountered.
    Type: Application
    Filed: December 8, 2003
    Publication date: June 23, 2005
    Applicant: Intel Corporation (a Delaware corporation)
    Inventors: Kushagra Vaid, Suresh Marisetty, Yaron Shragai, Koichi Yamada, Rajendra Kuramkote, Scott Brenden