Patents by Inventor Yaroslaw A. Magera

Yaroslaw A. Magera has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5792594
    Abstract: A process for metallizing an integrated circuit chip to form an interconnecting pattern for the chip's input/output terminals, wherein the process can be performed while the chip is still a part of the wafer on which it is fabricated and before separation into individual chips. The invention uses photodefinable resins as masks that form permanent dielectric layers of a multilayer structure with which interconnecting paths and terminals are defined on the surface of the chip. The process further employs conversion techniques that enable the interconnecting paths to be formed from metals other than aluminum, such that the electrical performance of the chip is enhanced. The use of the photodefinable resins renders the process of this invention conducive to inline processing techniques, thereby reducing processing costs while promoting high throughput and short cycle times.
    Type: Grant
    Filed: April 1, 1996
    Date of Patent: August 11, 1998
    Assignee: Motorola, Inc.
    Inventors: Vernon L. Brown, Yaroslaw A. Magera
  • Patent number: 5545430
    Abstract: A method for metallizing selected areas of a two dielectric layered sequentially processed circuit board (100) involves exposing the resin A (204) by photo-definition. The resin A (204) contains 10% or less, by weight Cu.sub.2 O particles (300) mixed uniformly throughout the resin. The circuit board (100) is sprayed with a reduction solution to form catalytic islands (301) predominately of Cu.sup.0 or CuH. The circuit board (100) is then electrolessly plated to form conductors, pads or vias, where the resin A (204) has been exposed. The reduction solution includes a primary reducing agent, a secondary reducing agent and a capturing agent. The reduction solution preferably has a pH of 10 or greater. The primary reducing agent is preferably a borohydride. The secondary reducing agent is preferably an iodide and the capturing agent is a chelating agent preferably EDTA.
    Type: Grant
    Filed: December 2, 1994
    Date of Patent: August 13, 1996
    Assignee: Motorola, Inc.
    Inventors: Yaroslaw A. Magera, Jovica Savic, Vernon L. Brown
  • Patent number: 5162144
    Abstract: A unique process metallizes a substrate surface using a reducing agent including a borohydride to reduce, in a starved reaction, metal oxide particles (300) substantially uniformly distributed and at a controlled concentration in a particle-filled resin (204) to produce catalytic island areas (301). The catalytic island areas (301) formed have a surface resistivity greater than 10.sup.6 ohms per square. These catalytic island areas (301) are then electrolessly metallized to a predetermined thickness, such that adjacent catalytic island areas (301) are interconnected and form metallic features, such as pads, vias (213), and conductors (210, 211 and 212). The starved reaction limits the reduction of metal oxide particles (300) to catalytic island areas (301) and prevents migration of reduced metal beyond each of the exposed surfaces of particle-filled resin (204) which are to be metallized.
    Type: Grant
    Filed: August 1, 1991
    Date of Patent: November 10, 1992
    Assignee: Motorola, Inc.
    Inventors: Vernon L. Brown, Julia S. Johnson, Yaroslaw A. Magera