Abstract: A semiconductor memory device with an internal refresh circuit is disclosed. The internal refresh circuit includes a timer circuit which generates a refresh request signal in a shorter cycle at a high temperature and in a longer cycle at a low temperature. The cycle of a self-refresh mode can be thereby lengthened in a low temperature to reduce a power consumption in the self-refresh mode.

Abstract: The semiconductor memory device includes an internal refresh circuit and an input circuit composed of first and second transistors of a different conductivity type having gates connected in common to an external control signal input terminal and connected in series with each other. A third transistor is connected in series to the first and second transistors. The third transistor is deactivated when the internal refresh circuit, operates to carry out a self-refresh mode, thereby suppressing a power consumption in the input circuit.

Abstract: In a memory selectively operable in an active and a standby mode, a first oscillation signal of a first frequency is produced by an oscillator (35a or 35b) in the standby mode so as to reduce electric power consumption, instead of a second oscillation signal which is produced in the active mode and which has a second frequency higher than the first frequency. The first and the second oscillation signals are selectively supplied as a substrate voltage to a substrate (20) through a substrate voltage production circuit (36). The oscillator may comprise a first circuit portion (46 to 48) for oscillating the second oscillation signal and a capacitor circuit (51 to 53) connected to the first circuit portion through a second circuit portion (56 to 58) in the standby mode so as to generate the second oscillation signal.

Abstract: A memory device having a large memory capacity which can be utilized either as a random access memory or a serial access memory is disclosed. The memory device comprises memory cells arrayed in a matrix form and a shift register whose output is used for selecting the memory cells.