Patents by Inventor Yaska Sankar

Yaska Sankar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Techniques for automated sweeping of parameters in computer-aided design to achieve optimum performance and resource usage
    Patent number: 7594208
    Abstract: Techniques for optimizing the placement and synthesis of a circuit design on a programmable integrated circuit are provided. The performance of a circuit design is analyzed after it has been compiled with different values for selected input parameters. The input parameter values that produce the best results for an output metric are then chosen to synthesis and place the circuit design on the programmable integrated circuit. In one embodiment, the values of the output metrics are averaged for all test compiles that share the same input parameters, but different seeds. In another embodiment, the compile with the best output metrics, as determined by the user, are selected. These techniques allow a user to automatically trade off compile-time to get a better-optimized circuit.
    Type: Grant
    Filed: December 13, 2006
    Date of Patent: September 22, 2009
    Assignee: Altera Corporation
    Inventors: Terry Borer, Ian Chesal, James Schleicher, David Mendel, Mike Hutton, Boris Ratchev, Yaska Sankar, Babette van Antwerpen, Gregg Baeckler, Richard Yuan, Stephen Brown, Vaughn Betz, Kevin Chan
  • Techniques for automated sweeping of parameters in computer-aided design to achieve optimum performance and resource usage
    Patent number: 7181703
    Abstract: Techniques for optimizing the placement and synthesis of a circuit design on a programmable integrated circuit are provided. The performance of a circuit design is analyzed after it has been compiled with different values for selected input parameters. The input parameter values that produce the best results for an output metric are then chosen to synthesis and place the circuit design on the programmable integrated circuit. In one embodiment, the values of the output metrics are averaged for all test compiles that share the same input parameters, but different seeds. In another embodiment, the compile with the best output metrics, as determined by the user, are selected. These techniques allow a user to automatically trade off compile-time to get a better-optimized circuit.
    Type: Grant
    Filed: July 22, 2003
    Date of Patent: February 20, 2007
    Assignee: Altera Corporation
    Inventors: Terry Borer, Ian Chesal, James Schleicher, David Mendel, Mike Hutton, Boris Ratchev, Yaska Sankar, Babette van Antwerpen, Gregg Baeckler, Richard Yuan, Stephen Brown, Vaughn Betz, Kevin Chan