Patents by Inventor Yasoo Harada

Yasoo Harada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5932889
    Abstract: An undoped Al.sub.0.22 Ga.sub.0.78 As spacer layer having a large forbidden bandgap and an N-Al.sub.0.22 Ga.sub.0.78 As electron-supplying layer having a large forbidden bandgap are formed in order on an undoped GaAs buffer layer having a small forbidden bandgap, and InAs quantum boxes are provided in the Al.sub.0.22 Ga.sub.0.78 As spacer layer. The size of the InAs quantum box is about 150 .ANG. and the height is about 40 .ANG.. When a predetermined drain voltage is applied, electrons are accumulated in the InAs quantum boxes from a channel formed in the vicinity of the interface with the Al.sub.0.22 Ga.sub.0.78 As spacer layer in the GaAs buffer layer. Accordingly, a drain current will not flow almost at all even if a drain voltage is applied.
    Type: Grant
    Filed: November 20, 1995
    Date of Patent: August 3, 1999
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Kohji Matsumura, Yasoo Harada
  • Patent number: 5751027
    Abstract: A field effect semiconductor device includes an undoped In.sub.0.2 Ga.sub.0.8 As first low-noise drift layer, an undoped In.sub.x Ga.sub.1-x As (x=0.2-0) second low-noise drift layer and an n-type GaAs high-power drift layer in this order. The high-power drift layer includes a first high-power drift layer doped with n-type carrier at high concentration and a second high-power drift layer doped with n-type carrier at low concentration.
    Type: Grant
    Filed: November 10, 1995
    Date of Patent: May 12, 1998
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Minoru Sawada, Yasoo Harada
  • Patent number: 5751029
    Abstract: An undoped Al.sub.0.22 Ga.sub.0.78 As layer, an undoped In.sub.0.2 Ga.sub.0.8 As electron-drifting layer, and an undoped GaAs electron-supplying layer are formed in order on a GaAs substrate. An impurity-doped layer .delta.-doped with Si donor is formed in the GaAs electron-supplying layer. An n-Al.sub.0.22 Ga.sub.0.78 As layer and n.sup.+ -GaAs cap layers are formed in order on the GaAs electron-supplying layer. A source electrode and a drain electrode are formed on the n.sup.+ -GaAs cap layers and a gate electrode is formed on the n-Al.sub.0.22 Ga.sub.0.78 As layer.
    Type: Grant
    Filed: May 17, 1996
    Date of Patent: May 12, 1998
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Shigeharu Matsushita, Daijirou Inoue, Kohji Matsumura, Minoru Sawada, Yasoo Harada
  • Patent number: 5724459
    Abstract: A optical divider equally divides a optical carrier into first and second optical carriers. A 180.degree. divider divides an RF sub-carrier signal into first and second RF sub-carrier signals whose phases are 180.degree. inverted from each other. An electro-optic modulator modulates the first optical carrier with the first RF sub-carrier signal and outputs a first optical signal. An electro-optic modulator modulates the second optical signal with the second RF sub-carrier signal and outputs a second optical signal. Photodiodes convert the first and second optical signals transmitted by the optical fibers into first and second electric signals, respectively. A 180.degree. combiner inverts by 180.degree. the phase of the first electric signal and combines it with the second electric signal.
    Type: Grant
    Filed: July 3, 1996
    Date of Patent: March 3, 1998
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Seiichi Banba, Minoru Sawada, Yasoo Harada
  • Patent number: 5650642
    Abstract: A field effect semiconductor device comprises a first channel layer composed of an undoped semiconductor in which electrons mainly drift in low-noise operation and a second channel layer composed of a semiconductor of one conductivity type in which electrons mainly drift in high-power operation, a third channel layer being provided in the second channel layer or on the second channel layer on the opposite side of the first channel layer. The third channel layer is constituted by at least one semiconductor layer of the one conductivity type or undoped having a greater electron affinity than that of the second channel layer and having a smaller forbidden bandgap than that of the second channel layer. In another field effect semiconductor device, an undoped impurity diffusion preventing layer having an electron affinity approximately equal to that of the second channel layer is provided between the first channel layer and the second channel layer.
    Type: Grant
    Filed: March 8, 1995
    Date of Patent: July 22, 1997
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Minoru Sawada, Shigeharu Matsushita, Satoshi Terada, Emi Fujii, Yasoo Harada
  • Patent number: 5614814
    Abstract: A negative voltage generating circuit includes an oscillating unit constructed of a ring oscillator for outputting a pulse signal with a high frequency and a polarity inverting unit in which the pulse signal is inputted to charge negative voltage. This negative voltage generating circuit is miniaturized and outputs a stable negative voltage. Further, the negative voltage to be outputted can be controlled by varying a resistance value through a control of an FET in a voltage controlling unit.
    Type: Grant
    Filed: December 28, 1994
    Date of Patent: March 25, 1997
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Masao Nishida, Takayoshi Higashino, Yasoo Harada
  • Patent number: 5590412
    Abstract: A communication apparatus for use in a portable telephone is disclosed which has a transmit-receive common amplifier for amplifying a transmitted signal or received signal, and a mixer for frequency-mixing the transmitted signal or the received signal with a local oscillator output, wherein connection between the mixer and an input side of the amplifier and connection between the mixer and an output side of the amplifier are made by means of respective signal-path selector switches. During reception, a deep bias is applied to an FET of the transmit-receive common amplifier to reduce current consumption, and during transmission, a shallow bias is applied to the FET of the transmit-receive common amplifier for increased output.
    Type: Grant
    Filed: November 18, 1994
    Date of Patent: December 31, 1996
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Tetsuro Sawai, Hisanori Uda, Toshikazu Hirai, Toshikazu Imaoka, Yasoo Harada, Keiichi Honda, Masao Nishida
  • Patent number: 5585676
    Abstract: An IC chip characterized in that at least two input pads and at least two output pads are respectively disposed symmetrical to each other about the center of the IC chip, at least two input/output pads are disposed symmetrical to each other about the center, at least one supply voltage pad is disposed in each of four equal sections formed by longitudinally and laterally dividing the IC chip, and at least one control voltage pad is disposed in each of these four sections. The IC chip can be connected by bonding to various types of IC packages having different configurations of the pins only by mounting in a proper direction without causing the bonding wires to bridge over the other constituent elements or to cross each other.
    Type: Grant
    Filed: April 18, 1994
    Date of Patent: December 17, 1996
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Hisanori Uda, Tetsuro Sawai, Toshikazu Imaoka, Toshikazu Hirai, Yasoo Harada
  • Patent number: 5559457
    Abstract: A double-balanced mixer circuit which consumes less power, and is capable of operating on a low voltage power source, because an output of a first signal having a phase lag of 90.degree. from a first frequency signal and an output of a second signal having a phase lead of 90.degree. over the first frequency signal are provided by means of a first phase shifter, an output of a third signal having a phase lag of 90.degree. from a second frequency signal and an output of fourth signal having a phase lead of 90.degree. over the second frequency signal are provided by means of a second phase shifter, thereby generating a radio frequency signal by mixing the first signal and the third signal in a first dual gate circuit, and generating a radio frequency signal by mixing the second signal and the fourth signal in a second dual gate circuit.
    Type: Grant
    Filed: March 21, 1994
    Date of Patent: September 24, 1996
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Hisanori Uda, Tetsuro Sawai, Toshikazu Imaoka, Toshikazu Hirai, Yasoo Harada
  • Patent number: 5557141
    Abstract: A group III-V compound semiconductor doped with an impurity, having an undoped film of SiOx and a film for preventing the diffusion of Group V atoms (e.g., an SiN film) are formed on a crystal of Group III-V compound semiconductor in which the silicon in the SiOx film is diffused into the Group III-V compound semiconductor, thereby forming a doped layer.
    Type: Grant
    Filed: March 30, 1994
    Date of Patent: September 17, 1996
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Yasoo Harada, Shigeharu Matsushita, Satoshi Terada, Emi Fujii, Takashi Kurose, Takayoshi Higashino, Takashi Yamada, Akihito Nagamatsu, Daijirou Inoue, Kouji Matsumura
  • Patent number: 5528509
    Abstract: The S-parameters of a transistor are measured at a plurality of bias points, and using a tentatively decided load resistance value, the S-parameters on the load curve are examined, based on which the power gain and input/output power characteristics are obtained to determine the optimum load. Then, by using a linear simulator, input and output circuits are designed so that the optimum load can be realized.
    Type: Grant
    Filed: March 17, 1994
    Date of Patent: June 18, 1996
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Tetsuro Sawai, Shigeyuki Murai, Tsutomu Yamaguchi, Yasoo Harada
  • Patent number: 5477184
    Abstract: An FET switch used for switching between a first transmission path includes a plurality of FETs for the transmission of a low power signal received at an antenna and a second transmission path including a plurality of FETs for the transmission of a higher power signal to the antenna, wherein the first transmission path and the second transmission path have FET circuits of configurations different from each other and/or employ FETs of different characteristics.
    Type: Grant
    Filed: April 15, 1993
    Date of Patent: December 19, 1995
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Hisanori Uda, Yasoo Harada
  • Patent number: 5404032
    Abstract: A novel field-effect semiconductor device having both low-noise and high-output operating characteristics has a first semiconductor buffer layer, an undoped second semi-conductor layer, an undoped third semiconductor layer the forbidden band gap of which increases from the substrate to the electrode side, a fourth semiconductor layer of one conductivity type, and a fifth semiconductor layer of undoped type or one conductivity type, formed one on top of another in this order on a semiconductor substrate. When the gate potential is deep, electrons mostly travel through the undoped second and third semiconductor layers, the device exhibiting superior low-noise characteristic; when the gate potential is shallow, electrons mostly travel through the highly doped fourth semiconductor layer, the device thus achieving high output characteristic.
    Type: Grant
    Filed: August 20, 1993
    Date of Patent: April 4, 1995
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Minoru Sawada, Yasoo Harada
  • Patent number: 5350709
    Abstract: A method of doping a Group III-V compound semiconductor with an impurity, wherein after an undoped film of SiOx and a film for preventing the diffusion of Group V atoms (e.g., an SiN film) are formed in this order on a crystal of Group III-V compound semiconductor, the sample is subjected to at least one heat treatment to cause silicon in the SiOx film to diffuse into the Group III-V compound semiconductor, thereby forming a doped layer. Using this doped layer forming method, field-effect transistors, diodes, resistive layers, two-dimensional electron gas or one-dimensional quantum wires, zero-dimensional quantum boxes, electron wave interference devices, etc. are fabricated.
    Type: Grant
    Filed: June 10, 1993
    Date of Patent: September 27, 1994
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Yasoo Harada, Shigeharu Matsushita, Satoshi Terada, Emi Fujii, Takashi Kurose, Takayoshi Higashino, Takashi Yamada, Akihito Nagamatsu, Daijirou Inoue, Kouji Matsumura