Patents by Inventor Yassine El Khourassani

Yassine El Khourassani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10997107
    Abstract: A system on chip includes an interconnect circuit including at least p input interfaces and at least k output interfaces, p source devices respectively coupled to the p input interfaces and k access ports respectively coupled to the k output interfaces and belonging to a target that includes one or more target devices. Each source device is configured to deliver transactions to the target via one of the access ports. An associated memory of each access port is configured to temporarily store the transactions received by the access port. The target is configured to deliver, for each access port, a fill signal representative of a current fill level of its associated memory. A control circuit is configured to receive the fill signals from the access ports and select the access ports eligible to receive a transaction depending on the current fill levels.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: May 4, 2021
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Yassine El Khourassani, Patrick Valdenaire, Emmanuel Ardichvili
  • Patent number: 10740141
    Abstract: A system on chip includes an interconnect circuit having an input interface and a number of output interfaces. A source device is coupled to the input interface. A target device includes a sectorized addressable memory space and a number of access ports respectively coupled to the output interfaces. The source device is configured to deliver a transaction containing an address word to the target device.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: August 11, 2020
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Yassine El Khourassani, Patrick Valdenaire, Emmanuel Ardichvili
  • Patent number: 10698843
    Abstract: An interconnect circuit includes a plurality of input interfaces and a plurality of output interfaces. A plurality of source devices are respectively coupled to the input interfaces. A target device has a plurality of access ports respectively coupled to the output interfaces. Each source device is configured to deliver transactions to the target device. Programmable control circuit is configured to deliver, to the interconnect circuit, a control word designating an access port assigned to this source device. The interconnect circuit is configured to route the transaction from the corresponding input interface to the output interface that is coupled to this access port and to deliver the transaction to the access port, the content of each transaction delivered to an access port being identical to the content of the corresponding transaction delivered by the source equipment whatever the selected access port.
    Type: Grant
    Filed: February 13, 2019
    Date of Patent: June 30, 2020
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Yassine El Khourassani, Patrick Valdenaire, Emmanuel Ardichvili
  • Publication number: 20200026679
    Abstract: A system on chip includes an interconnect circuit including at least p input interfaces and at least k output interfaces, p source devices respectively coupled to the p input interfaces and k access ports respectively coupled to the k output interfaces and belonging to a target that includes one or more target devices. Each source device is configured to deliver transactions to the target via one of the access ports. An associated memory of each access port is configured to temporarily store the transactions received by the access port. The target is configured to deliver, for each access port, a fill signal representative of a current fill level of its associated memory. A control circuit is configured to receive the fill signals from the access ports and select the access ports eligible to receive a transaction depending on the current fill levels.
    Type: Application
    Filed: July 8, 2019
    Publication date: January 23, 2020
    Inventors: Yassine El Khourassani, Patrick Valdenaire, Emmanuel Ardichvili
  • Publication number: 20190317799
    Abstract: A system on chip includes an interconnect circuit having an input interface and a number of output interfaces. A source device is coupled to the input interface. A target device includes a sectorized addressable memory space and a number of access ports respectively coupled to the output interfaces. The source device is configured to deliver a transaction containing an address word to the target device.
    Type: Application
    Filed: March 22, 2019
    Publication date: October 17, 2019
    Inventors: Yassine El Khourassani, Patrick Valdenaire, Emmanuel Ardichvili
  • Publication number: 20190266108
    Abstract: An interconnect circuit includes a plurality of input interfaces and a plurality of output interfaces. A plurality of source devices are respectively coupled to the input interfaces. A target device has a plurality of access ports respectively coupled to the output interfaces. Each source device is configured to deliver transactions to the target device. Programmable control circuit is configured to deliver, to the interconnect circuit, a control word designating an access port assigned to this source device. The interconnect circuit is configured to route the transaction from the corresponding input interface to the output interface that is coupled to this access port and to deliver the transaction to the access port, the content of each transaction delivered to an access port being identical to the content of the corresponding transaction delivered by the source equipment whatever the selected access port.
    Type: Application
    Filed: February 13, 2019
    Publication date: August 29, 2019
    Inventors: Yassine El Khourassani, Patrick Valdenaire, Emmanuel Ardichvili