Abstract: A programmable digital black level calibration circuit comprises a combining circuit, a digital programmable gain amplifier (PGA), and a black level feedback circuit. The combining circuit combines a digital image signal for optical black (OB) pixels and a feedback signal and outputs a digital PGA input signal. The PGA amplifies the digital PGA input signal by a PGA gain value and outputs a digital PGA output signal. The black level feedback circuit receives the digital PGA output signal and a target black level and in response outputs the feedback signal such that a black level of the OB pixels is calibrated with respect to the target black level. The programmable digital black level calibration circuit calibrates the black level in pure digital domain using signed data buses. The target black level is adjustable to a desired positive or negative value independent from the PGA gain value.

Abstract: Preview mode low-resolution readouts occur, and then a shutter button on a camera is pressed, which causes an image sensor cleanout operation to occur. Following the cleanout, a high-resolution readout occurs. As rows of sensor values are read, the first rows are rows corresponding to a pre-defined horizontally-extending shielded area. There are no valid area sensor elements to either side of the horizontally-extending area. Data values read from the horizontally-extending area are used to determine optical black (OB) values that are then used to adjust the valid area values read out of the image sensor in that same frame. The same OB values are used throughout the adjusting of the valid area values of the entire frame. No values from the preview readouts are used in the OB value determination, so there is a clean break between the preview mode OB level and the high-resolution capture OB level.

Abstract: A versatile analog front end and timing generator (AFE/TG) integrated circuit has output modes wherein multiple identical AFE/TGs output digitized sensor data to a single digital image processor (DIP) without intervening discrete multiplexing circuitry. In one embodiment, the AFE/TG is operable in either a bit slice mode or a time slice mode. In the bit slice mode, each of the multiple AFE/TGs sections up a word of pixel information into subsets of bits, and then communicates the subsets in parallel, one subset after another, across point-to-point connections to corresponding terminals of the DIP. The DIP captures the subsets of bits, and reassembles the subsets to recreate the word of pixel information. Each of the multiple AFE/TGs communicates words of pixel information to a different set of terminals on the DIP in this way, thereby avoiding timing complications, loading and/or expense associated with communicating the pixel information using time multiplexing techniques.

Abstract: A camera has a continuous full-resolution burst mode wherein a sequence of full-resolution images is captured, is image processed by a pipeline of dedicated hardware image processing engines, is zoomed by a zoom engine, is compressed by a compression engine, and is stored into nonvolatile storage as a sequence of discrete files. The capturing of images and the storing of files continues at a rate of at least three frames per second until the user indicates burst mode operation is to stop or until nonvolatile storage becomes filled. Although the camera has a buffer memory into which raw sensor data is placed before image processing, the number of images that can be captured in a single burst is not limited by the size of the buffer memory. The cost of a consumer market camera having continuous burst mode capability is therefore reduced by reducing the required amount of buffer memory.

Abstract: A versatile analog front end and timing generator (AFE/TG) integrated circuit is capable of supplying horizontal and vertical timing signals to a large number of disparate image sensors. In a first novel aspect, the AFE/TG includes an output mode wherein multiple identical AFE/TGs output digitized sensor data to a single digital image processor (DIP) without intervening multiplexing circuitry. In a second novel aspect, the AFE/TG includes a processor that executes a program. Execution of the program controls the detailed timing of horizontal and vertical timing signals output from the AFE/TG. At boot time, the program is loaded into the AFE/TG via a serial bus. In a third novel aspect, the processor is clocked by a clock signal with a relatively long clock period. A DLL and associated set/reset circuitry allows the processor to generate and control timing signals with a resolution substantially greater than clock period of the processor.

Abstract: A programmable digital black level calibration circuit comprises a combining circuit, a digital programmable gain amplifier (PGA), and a black level feedback circuit. The combining circuit combines a digital image signal for optical black (OB) pixels and a feedback signal and outputs a digital PGA input signal. The PGA amplifies the digital PGA input signal by a PGA gain value and outputs a digital PGA output signal. The black level feedback circuit receives the digital PGA output signal and a target black level and in response outputs the feedback signal such that a black level of the OB pixels is calibrated with respect to the target black level. The programmable digital black level calibration circuit calibrates the black level in pure digital domain using signed data buses. The target black level is adjustable to a desired positive or negative value independent from the PGA gain value.

Abstract: Preview mode low-resolution readouts occur, and then a shutter button on a camera is pressed, which causes an image sensor cleanout operation to occur. Following the cleanout, a high-resolution readout occurs. As rows of sensor values are read, the first rows are rows corresponding to a pre-defined horizontally-extending shielded area. There are no valid area sensor elements to either side of the horizontally-extending area. Data values read from the horizontally-extending area are used to determine optical black (OB) values that are then used to adjust the valid area values read out of the image sensor in that same frame. The same OB values are used throughout the adjusting of the valid area values of the entire frame. No values from the preview readouts are used in the OB value determination, so there is a clean break between the preview mode OB level and the high-resolution capture OB level.

Abstract: A versatile analog front end and timing generator (AFE/TG) integrated circuit has output modes wherein multiple identical AFE/TGs output digitized sensor data to a single digital image processor (DIP) without intervening discrete multiplexing circuitry. In one embodiment, the AFE/TG is operable in either a bit slice mode or a time slice mode. In the bit slice mode, each of the multiple AFE/TGs sections up a word of pixel information into subsets of bits, and then communicates the subsets in parallel, one subset after another, across point-to-point connections to corresponding terminals of the DIP. The DIP captures the subsets of bits, and reassembles the subsets to recreate the word of pixel information. Each of the multiple AFE/TGs communicates words of pixel information to a different set of terminals on the DIP in this way, thereby avoiding timing complications, loading and/or expense associated with communicating the pixel information using time multiplexing techniques.

Abstract: A versatile analog front end and timing generator (AFE/TG) integrated circuit is capable of supplying horizontal and vertical timing signals to a large number of disparate image sensors. In a first novel aspect, the AFE/TG includes an output mode wherein multiple identical AFE/TGs output digitized sensor data to a single digital image processor (DIP) without intervening multiplexing circuitry. In a second novel aspect, the AFE/TG includes a processor that executes a program. Execution of the program controls the detailed timing of horizontal and vertical timing signals output from the AFE/TG. At boot time, the program is loaded into the AFE/TG via a serial bus. In a third novel aspect, the processor is clocked by a clock signal with a relatively long clock period. A DLL and associated set/reset circuitry allows the processor to generate and control timing signals with a resolution substantially greater than clock period of the processor.