Abstract: The present disclosure relates to an imaging element and a method for controlling an imaging element, an imaging apparatus, and an electronic apparatus that can reduce the size of the imaging element and can reduce power consumption. First, a gray code corresponding to a P-phase pixel signal of each pixel is converted into a binary code. Then, a difference between a binary code corresponding to the converted same bit and a binary code of the pixel signal in which all bits are 0 and which is latched in a temporary latch is continuously calculated and is latched as the binary code of the P-phase pixel signal in the temporary latch. Then, a gray code corresponding to a D-phase pixel signal of each pixel is converted into a binary code. Then, a difference between a binary code corresponding to the converted same bit and the binary code of P-phase the pixel signal which is latched in the temporary latch is continuously calculated. The present disclosure can be applied to an imaging apparatus.

Abstract: The present disclosure relates to an imaging element and a method for controlling an imaging element, an imaging apparatus, and an electronic apparatus that can reduce the size of the imaging element and can reduce power consumption. First, a gray code corresponding to a P-phase pixel signal of each pixel is converted into a binary code. Then, a difference between a binary code corresponding to the converted same bit and a binary code of the pixel signal in which all bits are 0 and which is latched in a temporary latch is continuously calculated and is latched as the binary code of the P-phase pixel signal in the temporary latch. Then, a gray code corresponding to a D-phase pixel signal of each pixel is converted into a binary code. Then, a difference between a binary code corresponding to the converted same bit and the binary code of P-phase the pixel signal which is latched in the temporary latch is continuously calculated. The present disclosure can be applied to an imaging apparatus.

Abstract: The present technology relates to an image pickup device and an electronic apparatus capable of preventing degradation of the picture quality. A plurality of current sources can be selectively connected to an output terminal for outputting a reference signal having a level that varies, and a plurality of terminating resistors are connected to the output terminal. The terminating resistors that are to supply current of current sources that are connected to the output terminal are connected by a plurality of switches, and current of current sources that are not connected to the output terminal is supplied to the switches. The present technology can be applied, for example, to image pickup devices that perform AD conversion using a reference signal and so forth.

Abstract: The present technology relates to an image pickup device and an electronic apparatus capable of preventing degradation of the picture quality. A plurality of current sources can be selectively connected to an output terminal for outputting a reference signal having a level that varies, and a plurality of terminating resistors are connected to the output terminal. The terminating resistors that are to supply current of current sources that are connected to the output terminal are connected by a plurality of switches, and current of current sources that are not connected to the output terminal is supplied to the switches. The present technology can be applied, for example, to image pickup devices that perform AD conversion using a reference signal and so forth.

Abstract: The present disclosure relates to a solid state image sensor and an electronic apparatus capable of performing a gain transition at high speed. A ramp generation circuit includes sample hold circuits and ramp generation DACs, the number of which depends on kinds of required gains (for example, two kinds, i.e. a low gain and a high gain). Then, the two sample hold circuits can individually hold gain DAC output voltages at the different gains. This enables a switch to the ramp generation DAC holding the required gain voltage by means of a ramp selection signal. The present disclosure can be applied, for example, to a CMOS solid state image sensor that is used for an imaging device.

Abstract: A counter configured to perform counting at both edges of an input clock to output an additional value or a subtraction value for a previous count value and a next count value includes a first latch circuit that latches the input clock, a second latch circuit that latches an output from the first latch circuit, a holding section that holds data of the 0th bit of a count value, and a correction section that performs count correction on data of the first and subsequent bits of the count value on the basis of an output of the second latch circuit.

Abstract: The present disclosure relates to a solid state image sensor and an electronic apparatus capable of performing a gain transition at high speed. A ramp generation circuit includes sample hold circuits and ramp generation DACs, the number of which depends on kinds of required gains (for example, two kinds, i.e. a low gain and a high gain). Then, the two sample hold circuits can individually hold gain DAC output voltages at the different gains. This enables a switch to the ramp generation DAC holding the required gain voltage by means of a ramp selection signal. The present disclosure can be applied, for example, to a CMOS solid state image sensor that is used for an imaging device.

Abstract: A solid-state imaging device having an analog-digital converter, and an analog-digital conversion method are described herein. An example of a solid-state imaging device comprises a bit inconsistency prevention section configured to prevent bit inconsistency between output of a low-level bit latch section and a high-level bit counting section.

Abstract: The present invention relates to a column A/D converter, column A/D conversion method, imaging device, and camera system that can reduce the amount of IR drop by dispersing the current consumed during the count operation, mitigate the counter characteristic degradation, readily reduce the amount of fluctuation in the power source voltage, and achieve operation at a low power source voltage. The column A/D converter includes a plurality of column processing units including an A/D conversion function, a plurality of counters configured to generate digital codes in response to a reference clock and arranged corresponding to each or a set of the column processing units, and a count start offset unit configured to trigger a pseudo count operation in each of the counters and to offset a count start code for at least two or more counters among the plurality of counters before the reference clock is supplied to the counters.

Abstract: A signal processing circuit includes: a reference signal generating circuit that generates a reference signal of a ramp waveform of which a voltage value varies with the lapse of time by changing a current; and a signal processing unit including a plurality of processing sections that process the reference signal as a ramp wave and a potential of a supplied analog signal, wherein the reference signal processing circuit has a function of adjusting an offset of the reference signal by adjusting the current from the time of starting the generation of the reference signal or adjusting the level of the reference signal at least at the time of starting the generation of the reference signal.

Abstract: The present invention relates to a column A/D converter, column A/D conversion method, imaging device, and camera system that can reduce the amount of IR drop by dispersing the current consumed during the count operation, mitigate the counter characteristic degradation, readily reduce the amount of fluctuation in the power source voltage, and achieve operation at a low power source voltage. The column A/D converter includes a plurality of column processing units including an A/D conversion function, a plurality of counters configured to generate digital codes in response to a reference clock and arranged corresponding to each or a set of the column processing units, and a count start offset unit configured to trigger a pseudo count operation in each of the counters and to offset a count start code for at least two or more counters among the plurality of counters before the reference clock is supplied to the counters.

Abstract: A counter configured to perform counting at both edges of an input clock to output an additional value or a subtraction value for a previous count value and a next count value includes a first latch circuit that latches the input clock, a second latch circuit that latches an output from the first latch circuit, a holding section that holds data of the 0th bit of a count value, and a correction section that performs count correction on data of the first and subsequent bits of the count value on the basis of an output of the second latch circuit.

Abstract: A solid-state imaging device having an analog-digital converter, and an analog-digital conversion method are described herein. An example of a solid-state imaging device comprises a bit inconsistency prevention section configured to prevent bit inconsistency between output of a low-level bit latch section and a high-level bit counting section.

Abstract: A solid-state imaging device having an analog-digital converter, and an analog-digital conversion method are described herein. An example of a solid-state imaging device includes a bit inconsistency prevention section configured to prevent bit inconsistency between output of a low-level bit latch section and a high-level bit counting section.

Abstract: A counter configured to perform counting at both edges of an input clock to output an additional value or a subtraction value for a previous count value and a next count value includes a first latch circuit that latches the input clock, a second latch circuit that latches an output from the first latch circuit, a holding section that holds data of the 0th bit of a count value, and a correction section that performs count correction on data of the first and subsequent bits of the count value on the basis of an output of the second latch circuit.

Abstract: An A/D conversion circuit in which a counter is made to be capable of performing counting at both edges of a clock, up/down count values can be switched while the up/down count values are held, and the duty of the counting operation is difficult to be distorted even with the both-edge counting, a solid-state image sensor, and a camera system.

Abstract: A solid-state image pickup device and a camera system in which: (1) counters are organized into a counter group and a memory group on a column-by-column basis; (2) in each column, the individual counters are cascade-connected between individual bits; (3) switches are provided at bit output portions of the individual counters; (4) connecting sides of the individual switches are commonly connected to a column-signal transfer line, and output sides of the switches are shared with the other individual bits; (5) inputs of memories (latch circuits), which store digital data for horizontal transfer, share the column-signal transfer line; and (6) outputs of the memories corresponding to the individual bits are connected via switches to data transfer signal lines wired so as to be orthogonal to the column-signal transfer line.

Abstract: A solid-state imaging device including: a pixel section formed by a matrix-like array of a plurality of pixels performing photoelectric conversion; and a pixel signal readout section reading out a pixel signal from the pixel section in units for reading each formed by a plurality of pixels, wherein the pixel signal readout section includes a column-parallel type ADC group formed by a plurality of analog-digital converters (ADCs) for performing A-D conversion of a pixel reset level, and a signal processing system, the signal processing system obtaining only an average value of results of A-D conversion of pixel reset levels for a plurality of pixels and automatically adjusting an input offset value for the conversion range of the ADCs such that the average value of pixel reset levels will be adequately positioned with respect to the A-D conversion range.

Abstract: A solid-state imaging including a comparing circuit, an inverting circuit, and a masking circuit, and that performs column parallel AD conversion processing of analog pixel signals output from a plurality of pixels arranged in a two-dimensional matrix form. The comparing circuit outputs a difference signal obtained by comparing each of the pixel signals outputted from the pixels with a reference signal having a ramp waveform. The inverting circuit inverts a logic of the difference signal outputted from the comparing circuit. The masking circuit masks an output of an output signal of the inverting circuit to a circuit in a subsequent stage during an input offset canceling period in which the comparing circuit cancels an input offset between the pixel signal and the reference signal.

Abstract: A counter configured to perform counting at both edges of an input clock to output an additional value or a subtraction value for a previous count value and a next count value includes a first latch circuit that latches the input clock, a second latch circuit that latches an output from the first latch circuit, a holding section that holds data of the 0th bit of a count value, and a correction section that performs count correction on data of the first and subsequent bits of the count value on the basis of an output of the second latch circuit.