Patents by Inventor Yasuaki Nakazato

Yasuaki Nakazato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240094923
    Abstract: A controller assigns a first plurality of blocks among a plurality of blocks provided in a non-volatile memory to a first area, assigns a second plurality of blocks to a second area, and assigns a third plurality of blocks to a third area. The controller uses each block assigned to the first area in a first mode, uses each block assigned to the second area in a second mode in which the number of bits of data written in each memory cell is larger than that in the first mode, and uses each block assigned to the third area in the first mode or the second mode. The controller writes data received from a host device to an area that corresponds to a designation from the host device out of the first area and the third area. The controller transcribes valid data written to the first area and the third area to the second area.
    Type: Application
    Filed: January 31, 2023
    Publication date: March 21, 2024
    Applicant: Kioxia Corporation
    Inventors: Takashi WAKUTSU, Yasuaki NAKAZATO, Takeshi NAKANO
  • Publication number: 20240061620
    Abstract: A memory system includes a non-volatile memory and a controller that includes a first memory and is configured to write log data to the first memory, including a history of commands for controlling the memory system. An information processing system includes the memory system and an information processing device configured to store an expected value and to transmit a signal that instructs the memory system to stop when a value of the log data transmitted from the memory system does not match the expected value. The expected value and the transmitted value are determined based on the log data of the memory system.
    Type: Application
    Filed: November 3, 2023
    Publication date: February 22, 2024
    Inventors: Takeshi NAKANO, Akihiko ISHIHARA, Shingo TANIMOTO, Yasuaki NAKAZATO, Shinji MAEDA, Minoru UCHIDA, Kenji SAKAUE, Koichi INOUE, Yosuke KINO, Takumi SASAKI, Mikio TAKASUGI, Kouji SAITOU, Hironori NAGAI, Shinya TAKEDA, Akihito TOUHATA, Masaru OGAWA, Akira AOKI
  • Patent number: 11853599
    Abstract: A memory system includes a non-volatile memory and a controller that includes a first memory and is configured to write log data to the first memory, including a history of commands for controlling the memory system. An information processing system includes the memory system and an information processing device configured to store an expected value and to transmit a signal that instructs the memory system to stop when a value of the log data transmitted from the memory system does not match the expected value. The expected value and the transmitted value are determined based on the log data of the memory system.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: December 26, 2023
    Assignee: Kioxia Corporation
    Inventors: Takeshi Nakano, Akihiko Ishihara, Shingo Tanimoto, Yasuaki Nakazato, Shinji Maeda, Minoru Uchida, Kenji Sakaue, Koichi Inoue, Yosuke Kino, Takumi Sasaki, Mikio Takasugi, Kouji Saitou, Hironori Nagai, Shinya Takeda, Akihito Touhata, Masaru Ogawa, Akira Aoki
  • Publication number: 20210303214
    Abstract: A memory system includes a non-volatile memory and a controller that includes a first memory and is configured to write log data to the first memory, including a history of commands for controlling the memory system. An information processing system includes the memory system and an information processing device configured to store an expected value and to transmit a signal that instructs the memory system to stop when a value of the log data transmitted from the memory system does not match the expected value. The expected value and the transmitted value are determined based on the log data of the memory system.
    Type: Application
    Filed: February 25, 2021
    Publication date: September 30, 2021
    Inventors: Takeshi NAKANO, Akihiko ISHIHARA, Shingo TANIMOTO, Yasuaki NAKAZATO, Shinji MAEDA, Minoru UCHIDA, Kenji SAKAUE, Koichi INOUE, Yosuke KINO, Takumi SASAKI, Mikio TAKASUGI, Kouji SAITOU, Hironori NAGAI, Shinya TAKEDA, Akihito TOUHATA, Masaru OGAWA, Akira AOKI
  • Publication number: 20160266825
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory including a first storage area; and a memory controller which receives first data from a host device to access the nonvolatile memory, and causes the first storage area to store therein log data based on the first data.
    Type: Application
    Filed: August 26, 2015
    Publication date: September 15, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Ryuta WASEDA, Takeshi NAKANO, Yasuaki NAKAZATO, Michio NAGAFUJI, Shigeo KURAKATA, Hideaki YAMAMOTO
  • Publication number: 20080046760
    Abstract: A storage device includes a secure region including a plurality of pages. Each of a plurality of pages includes a first storage region in which a plurality of data items is stored and a second storage region in which a plurality of identification data items corresponding respectively to the plurality of data items is stored.
    Type: Application
    Filed: June 27, 2007
    Publication date: February 21, 2008
    Inventor: Yasuaki NAKAZATO
  • Patent number: 5931147
    Abstract: There is disclosed a method of slicing a semiconductor ingot in which the ingot is pressed against a moving wire. A thinner portion of the wire is used at the beginning of slicing to cut a portion of the ingot where the cutting length is shorter than a predetermined length, and a thicker portion of the wire is used when the cutting length becomes longer than the predetermined length. Subsequently, a thinner portion of the wire is used when the slicing approaches to the end and the cutting length becomes shorter than a predetermined length. A portion of the wire used in previous slicing is used as the thinner portion. Alternatively, the thinner portion is formed through use of a die. The slicing method makes it possible to cut the ingot into a plurality of wafers having a uniform thickness.
    Type: Grant
    Filed: March 20, 1997
    Date of Patent: August 3, 1999
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Yasuaki Nakazato, Noriaki Kubota, Hisakazu Takano, Mitsufumi Koyama
  • Patent number: 5800251
    Abstract: A lapping apparatus and a method for effectively utilizing a regenerated abrasive fluid in the lapping process of works such as semiconductor wafers or quartz wafers without causing any damage such as scratches to the works.A work lapping method using a regenerated abrasive fluid prepared from a used abrasive fluid and a new abrasive fluid, which comprises the steps of preliminarily lapping a work using the regenerated abrasive fluid to a predetermined stock removal of the work, and finally lapping the preliminarily lapped work using the new abrasive fluid.
    Type: Grant
    Filed: March 21, 1997
    Date of Patent: September 1, 1998
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Yasuaki Nakazato, Kazuo Kubota, Hisakazu Takano
  • Patent number: 5554303
    Abstract: An improvement is proposed in the method for the preparation of a magnetic recording medium by forming a magnetic recording layer of a magnetic alloy on the surface of a non-magnetic substrate plate of, e.g., silicon so as to impart the magnetic recording medium with improved CSS (contact-start-stop) characteristics still without affecting the magnetic recording density. The improvement can be obtained by subjecting the surface of the substrate plate, prior to the formation of the magnetic recording layer, to a surface-roughening treatment which is performed either by a dry-process such as plasma etching and reactive ion etching or by a wet-process of anisotropic etching by using an aqueous solution of sodium or potassium hydroxide as the anisotropic etching solution. In particular, the plasma etching or reactive ion etching is conducted in the presence of a particulate scattering source body of aluminum, etc.
    Type: Grant
    Filed: March 2, 1995
    Date of Patent: September 10, 1996
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Hideo Kaneko, Katsushi Tokunaga, Yoshio Tawara, Noboru Tamai, Yasuaki Nakazato
  • Patent number: 5521781
    Abstract: Proposed is a substrate of a magnetic recording medium in the form of an annular disk made from a single crystal of silicon which is imparted with greatly improved mechanical strengths to withstand mechanical shocks and high-velocity revolution. Different from conventional annular disks as formed by a mechanical working to form the outer contour and the circular center opening, the peripheral surfaces of the inventive annular disk are freed from the work-stressed surface layer by a chemical etching treatment undertaken after the mechanical working.
    Type: Grant
    Filed: May 22, 1995
    Date of Patent: May 28, 1996
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Hideo Kaneko, Yasuaki Nakazato, Toyofumi Aoki, Itsuo Kuroyanagi
  • Patent number: 5395788
    Abstract: The present invention provides a method of making a semiconductor substrate having an SOI structure by temporarily bonding together two wafers having different thermal expansion coefficients to allow thinning of at least one of the wafers by chemical and/or mechanical treatment(s) to reduce the risk of strain, separation, cracks to the wafers followed by one or more heat treating steps to fully bond the wafers together. The method can produce semiconductor substrate having an SOI structure which can provide a silicon layer thin enough to allow various integrated circuits, or TFL-LCD or the like to be formed.
    Type: Grant
    Filed: September 3, 1993
    Date of Patent: March 7, 1995
    Assignee: Shin Etsu Handotai Co., Ltd.
    Inventors: Takao Abe, Yasuaki Nakazato, Atsuo Uchiyama
  • Patent number: 5266824
    Abstract: The present invention provides a semiconductor substrate which is formed by bonding wafers together by heat treatment without causing the substrate to be thermally damaged to have thermal strain, separation, cracks, etc. due to the difference in the thermal expansion coefficient of the wafers, and particularly a semiconductor substrate having an SOI structure which can provide a silicon film thin enough to allow various integrated circuits or TFT-LCD to be formed In the present invention, after wafers are bonded temporarily in a low temperature range, one of the wafers is made thin by chemical treatment, then the wafers were bonded fully by heat treatment in a temperature range (where the thermal expansion coefficient of the wafer are not affected) higher than the above low temperature range, and then said one wafer can be made thinner by mechanical grinding or polishing mechano-chemically.
    Type: Grant
    Filed: March 16, 1992
    Date of Patent: November 30, 1993
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Takao Abe, Yasuaki Nakazato, Atsuo Uchiyama
  • Patent number: 5232870
    Abstract: A bonded wafer enjoying high strength of bonding of component wafers thereof is produced by a method which comprises causing the surfaces for mutual attachment of two semiconductor wafers to be irradiated with an ultraviolet light in an atmosphere of oxygen immediately before the two semiconductor wafers are joined to each other. One of the two semiconductor wafers to be used for the bonded wafer optionally has an oxide film formed on one surface thereof. One of the component wafers of the bonded wafer is optionally polished until the component wafer is reduced to a thin film.
    Type: Grant
    Filed: September 4, 1991
    Date of Patent: August 3, 1993
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Tatsuo Ito, Yasuaki Nakazato
  • Patent number: 5223080
    Abstract: A method for controlling the thickness of a single crystal thin-film silicon layer bonded on a dielectric substrate in a SOI substrate thereby effecting conversion of said single crystal silicon layer to a thin film is disclosed. To be more precise, said method comprises selectively and hypothetically dividing the entire surface of said single crystal silicon layer destined to undergo a chemical vapor-phase corrosion reaction for the sake of said conversion into necessary minute sections and, at the sametime, taking preparatory measurement of the thickness of said single crystal silicon layer in each of said minute sections, and effecting on each of said minute sections said conversion to a thin film by a chemical vapor-phase corrosion reaction adjusted in accordance with the measured thickness of layer. The conversion to a thin film is attained with the dispersion of thickness of the single crystal silicon layer controlled with high accuracy.
    Type: Grant
    Filed: November 27, 1991
    Date of Patent: June 29, 1993
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Yutaka Ohta, Masatake Katayama, Takao Abe, Yasuaki Nakazato
  • Patent number: 5213657
    Abstract: A Si single crystal thin film is classified according to the thickness into several areas such that the areas where the thin film is thicker is made oxide layer-free and the areas where the thin film is thinner is covered with oxide layer. Then, oxidation is conducted so that the thicker the thin film the lower the Si interface becomes, utilizing the different growth rates of the oxide layer in these areas. The thin film surface with a resulting staircase configuration is then leveled by the subsequent polishing treatment. In other method, oxide layer is formed in such way that the areas with a thicker thin film thickness will have a thinner oxide layer and the areas with a thinner thin film thickness will have a thicker oxide layer, and oxidation is conducted such that the thicker the thin film the lower the Si interface becomes.
    Type: Grant
    Filed: July 29, 1992
    Date of Patent: May 25, 1993
    Assignee: Shin-Etsu Handotai Kabushiki Kaisha
    Inventors: Takao Abe, Yasuaki Nakazato, Atsuo Uchiyama
  • Patent number: 5191738
    Abstract: A method of polishing a semiconductor wafer, wherein the semiconductor wafer bonded to a plate is polished to a desired thickness by pressing the semiconductor wafer against a rotating turntable side, and at the same time, a thickness regulating member, whose surface layer is made of a material slower to polish than the semiconductor wafer, is arranged on the plane of the plate to control the thickness of the semiconductor wafer. The matrix of the thickness regulating member is made of silicon and the surface layer facing said turntable is a silicon oxide film.
    Type: Grant
    Filed: October 25, 1991
    Date of Patent: March 9, 1993
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Yasuaki Nakazato, Hiroo Ogawara
  • Patent number: 5071785
    Abstract: A new method of preparing an exceedingly flat substrate for forming semiconductor devices having an SOI structure is disclosed.In this process at least a first wafer made of silicon single crystal is concavely warped beforehand. A second silicon single crystal wafer is bonded to the concavely warped side of the first wafer with an oxide film interposed between the first and the second wafers. Subsequently the wafers are subjected to polishing and/or etching so that the second wafer bonded is thinned into a thin film to prepare a substrate for forming semiconductor devices having a SOI structure.At this time the polishing and/or etching cause the bonded wafers to be warped convexly to offset the concavity of the first wafer, resulting in realization of a precisely flat substrate for forming semiconductor devices having an SOI structure.
    Type: Grant
    Filed: July 25, 1990
    Date of Patent: December 10, 1991
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Yasuaki Nakazato, Tokio Takei
  • Patent number: 5032544
    Abstract: A process for producing an SOI-structured semiconductor device substrate has the steps of: reducing the diameter of the one Si-monocrystal wafer of two bonded polished Si-monocrystal wafers to be slightly smaller than that of the other Si-monocrystal wafer so that the width of the annular margin defined between the bonded surfaces of the Si-monocrystal wafers is uniform; then forming an annular polishing guard on the cylindrical surface of the one wafer and the margin of the other wafer, the polishing guard having a predetermined thickness and being made of a material providing a polishing speed lower under the same condition than the one wafer; and then polishing the one wafer so as to make it in thin film. The polishing guard provides an accurate thickness control of the resulting Si-monocrystal thin film, in particular, even at a few micrometers level.
    Type: Grant
    Filed: August 13, 1990
    Date of Patent: July 16, 1991
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Tatsuo Ito, Yasuaki Nakazato
  • Patent number: 4388140
    Abstract: The invention provides a novel apparatus for the wet treatment, e.g. chemical etching treatment, of a plural number of wafer materials such as wafers of high purity silicon semiconductors. The apparatus comprises a liquid tub for containing the treatment liquid, e.g. etching solution, a pair of screw shafts horizontally held in the liquid tub in parallel with each other to be rotatable in the same direction at the same velocity to serve as a kind of screw conveyor and a traveling drum carriage mounted on the screw shafts as engaged with the threads of the shafts at the circular end plates so as to be rotated and transferred in the treatment liquid simultaneously as the screw shafts rotate.
    Type: Grant
    Filed: July 1, 1981
    Date of Patent: June 14, 1983
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Yasuaki Nakazato, Yasushi Miyazaki, Makoto Osuga, Masao Kodaira