Patents by Inventor Yasuaki Seki

Yasuaki Seki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9756732
    Abstract: A device embedded substrate (20), includes: an insulation layer (12) including an insulation resin material; an electric or electronic device (4) embedded in the insulation layer (12); a terminal (15) serving as an electrode included in the device (4); a conductor pattern (18) formed on the surface of the insulation layer (12); and a conducting via (21) for electrically connecting the conductor pattern (18) and the terminals (15) with each other. The conducting via (21) is made up of a large-diameter section (21a) having a large diameter and a small-diameter section (21b) having a smaller diameter than that of the large-diameter section (21a), in order starting from the conductor pattern (18) toward the terminal (15). A stepped section (17) is formed between the large-diameter section (21a) and the small-diameter section (21b). The large-diameter section (21a) is formed so as to penetrate a sheet-shaped glass cloth (11) disposed in the insulation layer (12).
    Type: Grant
    Filed: January 18, 2013
    Date of Patent: September 5, 2017
    Assignee: MEIKO ELECTRONICS CO., LTD.
    Inventors: Yasuaki Seki, Tomoyuki Nagata, Mitsuaki Toda
  • Publication number: 20150327369
    Abstract: A device embedded substrate (20), includes: an insulation layer (12) including an insulation resin material; an electric or electronic device (4) embedded in the insulation layer (12); a terminal (15) serving as an electrode included in the device (4); a conductor pattern (18) formed on the surface of the insulation layer (12); and a conducting via (21) for electrically connecting the conductor pattern (18) and the terminals (15) with each other. The conducting via (21) is made up of a large-diameter section (21a) having a large diameter and a small-diameter section (21b) having a smaller diameter than that of the large-diameter section (21a), in order starting from the conductor pattern (18) toward the terminal (15). A stepped section (17) is formed between the large-diameter section (21a) and the small-diameter section (21b). The large-diameter section (21a) is formed so as to penetrate a sheet-shaped glass cloth (11) disposed in the insulation layer (12).
    Type: Application
    Filed: January 18, 2013
    Publication date: November 12, 2015
    Applicant: MEIKO ELECTRONICS CO., LTD.
    Inventors: Yasuaki Seki, Tomoyuki Nagata, Mitsuaki Toda
  • Patent number: 6710260
    Abstract: In a manufacturing method of a printed circuit board comprising a process of forming a circuit pattern on the surface of the base substrate (13) of which surface is at least composed of an insulative material, a process of forming the insulative layer (15) composed of mixed composites of more than two kinds of organic resins having a different etching rate by a dry etching process on the surface of the base substrate (13) including the circuit pattern, a process of perforating the hole (17) on the insulative layer (15) by a laser beam, a process of roughing the surface of the insulative layer (15) by a dry etching process, a process of forming the conductive film (19) for a foundation of an electroplating process by a vacuum film forming method and a process of forming the conductive layer (20) on the conductive film (19) by an electroplating process so as to connect the conductive layer (20) with the circuit pattern (14) electrically.
    Type: Grant
    Filed: March 29, 2000
    Date of Patent: March 23, 2004
    Assignee: Victor Company of Japan, Ltd.
    Inventors: Yasuaki Seki, Takashi Ito, Shuji Mochizuki
  • Patent number: 6613987
    Abstract: Herein is disclosed an insulating resin composition for a multilayer printed-wiring board, comprising two or more kinds of resins which are different in etching rate by plasma treatment and which are not compatible with each other, so that the surface of the resulting insulating layer can be made uneven by the plasma treatment, whereby the bonding strength of the conductor layer to the said resulting insulating layer can be ensured, and heat resistance and electrically insulating properties required can be satisfied.
    Type: Grant
    Filed: March 31, 2000
    Date of Patent: September 2, 2003
    Assignee: Ajinomoto Co., Inc.
    Inventors: Yasuaki Seki, Takashi Ito, Shuji Mochizuki, Kiyonori Furuta, Toshihiko Hatajima
  • Publication number: 20030007332
    Abstract: Herein is disclosed an insulating resin composition for a multilayer printed-wiring board, comprising two or more kinds of resins which are different in etching rate by plasma treatment and which are not compatible with each other, so that the surface of the resulting insulating layer can be made uneven by the plasma treatment, whereby the bonding strength of the conductor layer to the said resulting insulating layer can be ensured, and heat resistance and electrically insulating properties required can be satisfied.
    Type: Application
    Filed: March 31, 2000
    Publication date: January 9, 2003
    Inventors: Yasuaki Seki, Takashi Ito, Shuji Mochizuki, Kiyonori Furuta, Toshihiko Hatajima
  • Publication number: 20020001699
    Abstract: In a manufacturing method of a printed circuit board comprising a process of coating insulative resin on a surface of a printed circuit board having a blind hole and a process of filling up the insulative resin in the blind hole, the printed circuit board coated with the insulative resin is kept in a low pressure atmosphere of 1.3 to 666 hPa, and then the insulative resin is hardened, so that the insulative resin is filled up in the blind hole appropriately.
    Type: Application
    Filed: July 20, 2001
    Publication date: January 3, 2002
    Applicant: Victor Company of Japan, Ltd.
    Inventors: Yasuaki Seki, Shigenori Shiratori, Kenji Suzuki
  • Patent number: 6284308
    Abstract: In a manufacturing method of a printed circuit board comprising a process of coating insulative thermosetting resin on a surface of a printed circuit board having a blind hole and a process of filling up the insulative thermosetting resin in the blind hole, the printed circuit board coated with the insulative thermosetting resin is kept in a low pressure atmosphere of 1.3 to 666 hPa, and then the insulative thermosetting resin is hardened, so that the insulative thermosetting resin is filled up in the blind hole appropriately.
    Type: Grant
    Filed: December 15, 1999
    Date of Patent: September 4, 2001
    Assignee: Victor Company of Japan, Ltd.
    Inventors: Yasuaki Seki, Shigenori Shiratori, Kenji Suzuki
  • Publication number: 20010008650
    Abstract: In a manufacturing method of a printed circuit board comprising a process of coating insulative resin on a surface of a printed circuit board having a blind hole and a process of filling up the insulative resin in the blind hole, the printed circuit board coated with the insulative resin is kept in a low pressure atmosphere of 1.3 to 666 hPa, and then the insulative resin is hardened, so that the insulative resin is filled up in the blind hole appropriately.
    Type: Application
    Filed: December 15, 1999
    Publication date: July 19, 2001
    Inventors: YASUAKI SEKI, SHIGENORI SHIRATORI, KENJI SUZUKI