Abstract: A PLL circuit comprises a reference signal generating unit for generating reference signals of different phases, variable frequency dividers for dividing the frequency of the output signal of a voltage-controlled oscillator (VCO) and thereby outputting feedback signals, and a phase comparator for comparing the phase of each feedback signal with that of the corresponding reference signal and thereby outputting phase comparison signals. When the output signal is synchronized with a preset frequency signal, at least one variable frequency divider of the variable frequency dividers is operated, and the operation of the other is stopped.

Abstract: A PLL circuit including a generating means (3) for generating a plurality of reference signals (fR1 to fR8) having mutually differing phases, a main frequency divider (30) dividing an output signal (fVCO) of a voltage-controlled oscillator (29) by a frequency-division ratio of N1, an auxiliary frequency divider (31) dividing an output (fV?) of the main frequency divider by a frequency-division ratio of N2, a distribution circuit (32) distributing an output (Q1a, Q2a, Q3a) of the auxiliary frequency divider as a plurality of feedback signals (fV1 to fV8), and phase comparators (12 to 19) comparing the reference signals with the feedback signals to output error signals (ER1 to ER8). Each of the main frequency divider and the auxiliary frequency divider is comprised of a variable frequency divider or a counter.

Abstract: A PLL circuit comprises a reference signal generating unit for generating reference signals of different phases, variable frequency dividers for dividing the frequency of the output signal of a voltage-controlled oscillator (VCO) and thereby outputting feedback signals, and a phase comparator for comparing the phase of each feedback signal with that of the corresponding reference signal and thereby outputting phase comparison signals. When the output signal is synchronized with a preset frequency signal, at least one variable frequency divider of the variable frequency dividers is operated, and the operation of the other is stopped.

Abstract: In a PLL device with a plurality of phase comparators, when one phase comparator has reached a locked state, this phase comparator is allowed to keep on delivering an output, while outputs of the other phase comparators are disabled. Accordingly, power consumption can be reduced. Furthermore, an error current output from a charge pump (109) connected to the phase comparators to output an error signal is reduced when lock approaches. Accordingly, lock failure can be avoided. Furthermore, a time constant of a low-pass filter (220) that receives the output of the charge pumps connected to the phase comparators is altered following alteration of the number of the phase comparators (212 to 219) that deliver their outputs. Accordingly, power consumption can be reduced, and also stability and converging speed are improved. Using distribution means (318) instead of frequency dividers provided for the phase comparators individually makes LSI implementation easy.

Abstract: A PLL circuit including a generating means (3) for generating a plurality of reference signals (fR1 to fR8) having mutually differing phases, a main frequency divider (30) dividing an output signal (fVCO) of a voltage-controlled oscillator (29) by a frequency-division ratio of N1, an auxiliary frequency divider (31) dividing an output (fV′) of the main frequency divider by a frequency-division ratio of N2, a distribution circuit (32) distributing an output (Q1a, Q2a, Q3a) of the auxiliary frequency divider as a plurality of feedback signals (fV1 to fV8), and phase comparators (12 to 19) comparing the reference signals with the feedback signals to output error signals (ER1 to ER8). Each of the main frequency divider and the auxiliary frequency divider is comprised of a variable frequency divider or a counter.

Abstract: A PLL device has a voltage-controlled oscillator, a reference generator that generates reference signals with different phases, and a main divider that divides the frequency of the output signal of the voltage-controlled oscillator by a frequency-division ratio N1. An auxiliary divider divides the frequency of the output of the main divider by a frequency-division ratio N2. A distribution circuit distributes the output of the auxiliary divider as feedback signals. Phase detectors compare the reference signals and the feedback signals, and generate error signals. Each of the main divider and the auxiliary divider has a programmable divider or a counter. The main divider and the auxiliary divider are both operative during start-up to shorten PLL lock-up time, and the auxiliary divider then powers down to reduce power consumption.

Abstract: A PLL circuit produces first to n-th (n being an integer equal to or greater than 2) reference signals. A first variable frequency divider divides the frequency of an output of a voltage-controlled oscillator to produce a first feedback signal. A second variable frequency divider divides the output of the voltage-controlled oscillator to produce second to n-th feedback signals. A phase comparator compares the phases of the first to the n-th reference signals with the phases of the first to the n-th feedback signals to produce first to n-th error signals. A controller produces a control signal from the error signals. The PLL circuit synchronizes the first reference signal with the first feedback signal in phase after the phase difference between at least one of the first to n-th reference signals and a corresponding feedback signal becomes smaller than a predetermined value. The frequency-division ratio of the second variable frequency divider is 1/n that of the first variable frequency divider.

Abstract: A PLL device includes a programmable frequency-division device 111 that divides the frequency of the output of a voltage-controlled oscillator 112, a reference signal generating means 105 that generates a first reference signal and a second reference signal having different phases, a first comparator 106 that compares the phases of the first reference signal and the output of the programmable frequency-division device 111, a second comparator 110 that compares the phases of the second reference signal and the output of the programmable frequency-division device 111, a detector 118 that detects the locked state, and a control unit 117. With this structure, when the state is not locked, phase comparisons are performed by a plurality of comparators at different timings, so the locking time is shortened because more than one phase comparison is performed in one period of the reference signal.

Abstract: The PLL device includes means (6) for generating a, plurality of reference signals (FR1, FR2, FR3, FR4) having mutually differing phases, a variable frequency divider (11, 12, 13, 14) for dividing, in synchronization with the phases of a plurality of the reference signals, a frequency of an output signal (FO) of a voltage-controlled oscillator (15) that produces a signal having a frequency responsive to a control voltage (CV) supplied to generate a plurality of feedback signals (FV1, FV2, FV3, FV4) having mutually differing phases, phase comparators (7, 17, 8, 18, 9, 19, 10, 20) for comparing phases between the reference signals and the feedback signals corresponding to the reference signals respectively to produce a plurality of error signals (ER1, ER2, ER3, ER4), a low-pass filter (21) for filtering the error signals output from the phase comparators to produce the control voltage, and a control means (16, 26, 27) for controlling the number of the phase comparators that output the error signals to the low-p

Abstract: In a PLL device with a plurality of phase comparators, when one phase comparator has reached a locked state, this phase comparator is allowed to keep on delivering an output, while outputs of the other phase comparators are disabled. Accordingly, power consumption can be reduced. Furthermore, an error current output from a charge pump (109) connected to the phase comparators to output an error signal is reduced when lock approaches. Accordingly, lock failure can be avoided. Furthermore, a time constant of a low-pass filter (220) that receives the output of the charge pumps connected to the phase comparators is altered following alteration of the number of the phase comparators (212 to 219) that deliver their outputs. Accordingly, power consumption can be reduced, and also stability and converging speed are improved. Using distribution means (318) instead of frequency dividers provided for the phase comparators individually makes LSI implementation easy.

Abstract: The PLL circuit (1) includes means (2) for producing a first to an n-th (n being an integer equal to or greater than 2) reference signals (FR1 to FR13), a first variable frequency-dividing means (8) for dividing, at a timing according to the phase of the first reference signal (FR1), the frequency of an output (VO) of a voltage-controlled oscillator (6) generating a signal having a frequency responsive to a supplied control voltage (CV) to produce a first feedback signal (FP1), a second variable frequency dividing means (9) for frequency dividing, at timings according to the phases of the second to the n-th reference signals (FR2 to FR13) the output (VO) of the voltage-controlled oscillator (6) to produce a second to an n-th feedback signals (FP2 to FP13), a phase comparing means (A1 to A13) for comparing the phases of the first to the n-th reference signals (FR1 to FR13) with the phases of the first to the n-th feedback signals (FP1 to FP13) to produce a first to an n-th error signals (ER1 to ER13) and a con

Abstract: A PLL device includes a programmable frequency-division device 111 that divides the frequency of the output of a voltage-controlled oscillator 112, a reference signal generating means 105 that generates a first reference signal and a second reference signal having different phases, a first comparator 106 that compares the phases of the first reference signal and the output of the programmable frequency-division device 111, a second comparator 110 that compares the phases of the second reference signal and the output of the programmable frequency-division device 111, a detector 118 that detects the locked state, and a control unit 117. With this structure, when the state is not locked, phase comparisons are performed by a plurality of comparators at different timings, so the locking time is shortened because more than one phase comparison is performed in one period of the reference signal.

Abstract: In a phase-locked loop with reference, feedback, and error signals, the trade-off between lock-up time and power dissipation is improved by one of the following methods: supplying a continuous error signal, instead of an intermittent error signal, to a charge pump during lock acquisition; employing a half-integer frequency divider and making multiple phase-and-frequency comparisons during each reference signal cycle; employing a prescaled feedback signal and making multiple phase-and-frequency comparisons during each reference signal cycle; providing multiple feedback loops and employing a selectable number of the loops during lock acquisition; and employing multiple feedback loops with prescaling of the reference and feedback signals.

Abstract: In a variable frequency divider capable of N+1/2 frequency division, a programmable frequency divider alternately frequency-divides an input signal by a frequency division ratio N (N being an integer) or by a frequency division ratio N+1. A first signal generating circuit generates a first signal in synchronism with an output signal of the programmable frequency division circuit. A second signal generating circuit generates a second signal which is identical to the first signal but delayed by half a period of the input signal. An output circuit alternately selects the first and second signals, and outputs the selected signal as frequency-divided signal. A delay circuit outputs a delayed signal identical to the first signal but delayed by one period of the input signal. A preset signal generating circuit alternately selects the delayed signal and the first signal, and presets the programmable frequency division circuit with the selected signal.

Abstract: A velocity control circuit for a motor 28 to drive a disc 2 of a constant linear velocity system, which phase-compares the reference frequency signal with a data signal reproduced from the disc 2 or a demodulated clock signal in synchronism with the data signal, whereby the phase comparison error output drive-controls the motor 28 including the starting thereof and the disc 2 is drive-controlled at constant linear velocity.

Abstract: A frequency synthesized multi-band receiver having a phase locked loop (PLL) including a voltage controlled oscillator (VCO) for producing the local oscillator frequency. The PLL includes a programmable divider for dividing the output of the VCO for comparison with a reference frequency in a phase detector to produce a voltage for controlling the output frequency of the VCO. Memory means are provided for storing information concerning the upper and lower frequency limits of the bands over which the receiver is to operate.

Abstract: A scanning type frequency synthesized receiver utilizing a voltage controlled oscillator (VCO) for producing a local oscillator signal. The control voltage for the VCO is provided in response to the division rate of a programmable divider. A control circuit programs the divider which control circuit operates to vary the divisor of the divider within a predetermined range as determined by information stored in a memory corresponding to a range of frequencies in a frequency band to be scanned and received by the receiver. Upon a command signal the control circuit operates to vary the divisor of the divider either up or down to cause the frequency of VCO, and thereby the receiver, to scan in a given direction and upon a signal being received the variation of the divider divisor and the receiver scanning is terminated.

Abstract: A multiple-band superheterodyne receiver, comprising a high frequency amplifier for receiving a high frequency signal, a local oscillator for providing an oscillation frequency signal the frequency of which is different by a given frequency difference from the received high frequency signal, a mixer for mixing these two frequency signals for providing an intermediate frequency signal, a band selecting switch, and means for setting the data concerning the frequency of a high frequency signal to be received, said local oscillator comprising a voltage controlled oscillator for providing an oscillation frequency signal the frequency of which is variable as a function of a given control voltage, a frequency divider for frequency dividing the output from the voltage controlled oscillator, a read only memory for storing the data concerning a plurality of frequency differences, each corresponding to one of said plurality of receiving frequency bands and responsive to the band selecting signal for selectively withdraw