Patents by Inventor Yasuaki Tsuchiya
Yasuaki Tsuchiya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240113367Abstract: A method for producing a power storage device includes placing a lid assembly that includes a lid and a terminal member integrated therewith via a resin member to close an opening portion of a case body with the lid, and laser-welding the opening portion of the case body and the peripheral portion of the lid over an entire circumference. In placing the lid assembly, a peripheral high-level region, in which a peripheral outer surface of the peripheral portion of the lid is located on the outer side relative to an opening end surface of the opening portion of the case body is provided in proximate long-side opening portions, close of the opening portion and proximate long-side peripheral portions of the peripheral portion.Type: ApplicationFiled: September 7, 2023Publication date: April 4, 2024Inventors: Yuki SATO, Yozo UCHIDA, Tsuyoshi EHARA, Syoichi TSUCHIYA, Masataka ASAI, Tsuyoshi ASANO, Masahiro UCHIMURA, Shigeru MATSUMOTO, Yasuaki NAGANO
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Publication number: 20240113366Abstract: A method for producing a power storage device includes forming a lid, forming a lid assembly, closing, and welding. In forming a lid, there is included forming, by forging, a protruding portion between a peripheral portion and an insertion-hole surrounding portion of the lid to block scattered light of a laser beam from being irradiated to a resin member, with a distance D from an end surface of the peripheral portion to a side surface of the protruding portion falling within 0.5t (D?0.5t) relative to a thickness t of the lid.Type: ApplicationFiled: September 7, 2023Publication date: April 4, 2024Inventors: Yuki SATO, Yozo UCHIDA, Tsuyoshi EHARA, Syoichi TSUCHIYA, Masataka ASAI, Tsuyoshi ASANO, Masahiro UCHIMURA, Shigeru MATSUMOTO, Yasuaki NAGANO
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Publication number: 20240113368Abstract: A method for producing a power storage device includes closing an opening portion of a case body with a lid of a lid assembly, and laser-welding the opening portion of the case body and a peripheral portion of the lid over their entire circumference. A resin member has an outer surface including a scattered light-reached surface to which scattered light of a laser beam directly reaches, at least a part of the scattered light-reached surface including a smoothed region having a surface roughness of 0.6 ?m or less.Type: ApplicationFiled: September 11, 2023Publication date: April 4, 2024Inventors: Yuki SATO, Yozo UCHIDA, Tsuyoshi EHARA, Syoichi TSUCHIYA, Masataka ASAI, Tsuyoshi ASANO, Masahiro UCHIMURA, Shigeru MATSUMOTO, Yasuaki NAGANO
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Publication number: 20230097408Abstract: A semiconductor device includes an insulating layer, a first conductive film, a second conductive film and a thin-film resistor. The insulating layer has a penetrating portion. The first conductive film is formed in the penetrating portion such that a recess is formed at an upper part of the penetration portion. The second conductive film is formed on an upper surface of the first conductive film and an inner surface of the penetrating portion. The thin-film resistor includes silicon and metal. The thin-film resistor is formed on the second conductive film and the insulating layer.Type: ApplicationFiled: September 29, 2021Publication date: March 30, 2023Inventors: Nozomi ITO, Kazuyoshi MAEKAWA, Yuji TAKAHASHI, Yasuaki TSUCHIYA, Nobuhito SHIRAISHI
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Patent number: 9779992Abstract: A method of manufacturing a semiconductor device includes forming a first via having a first diameter in a first main surface of a semiconductor substrate having a first thickness, after forming a first insulating film on a bottom surface and a side surface of the first via, forming a first through electrode inside the first via a first barrier metal film, after forming the first through electrode, processing the semiconductor substrate from a second main surface on an opposite side of the first main surface to reduce the first thickness of the semiconductor substrate to a second thickness thinner than the first thickness, after processing the semiconductor substrate, forming a third insulating film on the second main surface of the semiconductor substrate, and after forming the third insulating film, sequentially processing the third insulating film and the semiconductor substrate.Type: GrantFiled: February 2, 2016Date of Patent: October 3, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Ryohei Kitao, Yasuaki Tsuchiya
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Publication number: 20160148841Abstract: A method of manufacturing a semiconductor device includes forming a first via having a first diameter in a first main surface of a semiconductor substrate having a first thickness, after forming a first insulating film on a bottom surface and a side surface of the first via, forming a first through electrode inside the first via a first barrier metal film, after forming the first through electrode, processing the semiconductor substrate from a second main surface on an opposite side of the first main surface to reduce the first thickness of the semiconductor substrate to a second thickness thinner than the first thickness, after processing the semiconductor substrate, forming a third insulating film on the second main surface of the semiconductor substrate, and after forming the third insulating film, sequentially processing the third insulating film and the semiconductor substrate.Type: ApplicationFiled: February 2, 2016Publication date: May 26, 2016Inventors: RYOHEI KITAO, Yasuaki Tsuchiya
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Patent number: 9275935Abstract: Technology that achieves high integration of a semiconductor device employing TSV technology is provided. A through electrode is configured by a small-diameter through electrode having a first diameter and being formed on a main surface side of a semiconductor wafer, and a large-diameter through electrode having a second diameter larger than the above-described first diameter and being formed on a back surface side of the semiconductor wafer, and the small-diameter through electrode is arranged inside the large-diameter through electrode in a planar view so that a center position of the small-diameter through electrode and a center position of the large-diameter through electrode do not overlap with each other in the planar view.Type: GrantFiled: August 7, 2013Date of Patent: March 1, 2016Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Ryohei Kitao, Yasuaki Tsuchiya
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Publication number: 20140061940Abstract: Technology that achieves high integration of a semiconductor device employing TSV technology is provided. A through electrode is configured by a small-diameter through electrode having a first diameter and being formed on a main surface side of a semiconductor wafer, and a large-diameter through electrode having a second diameter larger than the above-described first diameter and being formed on a back surface side of the semiconductor wafer, and the small-diameter through electrode is arranged inside the large-diameter through electrode in a planar view so that a center position of the small-diameter through electrode and a center position of the large-diameter through electrode do not overlap with each other in the planar view.Type: ApplicationFiled: August 7, 2013Publication date: March 6, 2014Applicant: Renesas Electronics CorporationInventors: Ryohei KITAO, Yasuaki Tsuchiya
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Patent number: 8512540Abstract: An objective of this invention is to reliably form a plating film. The following two steps are sequentially conducted: a first step of connecting a film-formation surface of a wafer 109 to a cathode electrode 107, making the film-formation surface inclined from the surface of a plating solution 103 and immersing the wafer 109 into the plating solution 103 with applying a first current between the cathode electrode 107 and an Cu anode electrode 105 disposed in the plating solution 103, and second step of, after immersing the film-formation surface in the plating solution 103, applying a second current between the cathode electrode 107 and the Cu anode electrode 105 to form a metal film on the film-formation surface by electrolytic plating. In the first step, the first current is controlled on the basis of an inclination angle between the liquid surface and the film-formation surface.Type: GrantFiled: March 9, 2011Date of Patent: August 20, 2013Assignee: Renesas Electronics CorporationInventors: Akira Furuya, Yasuaki Tsuchiya
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Patent number: 8329584Abstract: A post-CMP cleaning process of a copper layer is to be performed as follows. An alkaline aqueous solution, a polycarboxylic acid, BTA, and an alkaline aqueous solution are sequentially brought into contact with a primary surface of a silicon substrate over which the copper layer is provided.Type: GrantFiled: June 2, 2011Date of Patent: December 11, 2012Assignee: Renesas Electronics CorporationInventors: Toshiyuki Takewaki, Manabu Iguchi, Daisuke Oshida, Hironori Toyoshima, Masayuki Hiroi, Takuji Onuma, Hiroaki Nanba, Ichiro Honma, Mieko Hasegawa, Yasuaki Tsuchiya, Toshiji Taiji, Takaharu Kunugi
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Publication number: 20110230051Abstract: A post-CMP cleaning process of a copper layer is to be performed as follows. An alkaline aqueous solution, a polycarboxylic acid, BTA, and an alkaline aqueous solution are sequentially brought into contact with a primary surface of a silicon substrate over which the copper layer is provided.Type: ApplicationFiled: June 2, 2011Publication date: September 22, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Toshiyuki TAKEWAKI, Manabu IGUCHI, Daisuke OSHIDA, Hironori TOYOSHIMA, Masayuki HIROI, Takuji ONUMA, Hiroaki NANBA, Ichiro HONMA, Mieko HASEGAWA, Yasuaki TSUCHIYA, Toshiji TAIJI, Takaharu KUNUGI
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Publication number: 20110155578Abstract: An objective of this invention is to reliably form a plating film. The following two steps are sequentially conducted: step 101 of connecting a film-formation surface of a wafer 109 to a cathode electrode 107, making the film-formation surface inclined from the surface of a plating solution 103 and immersing the wafer 109 into the plating solution 103 with applying a first current between the cathode electrode 107 and an Cu anode electrode 105 disposed in the plating solution 103, and step 103 of, after immersing the film-formation surface in the plating solution 103, applying a second current between the cathode electrode 107 and the Cu anode electrode 105 to form a metal film on the film-formation surface by electrolytic plating. In step 101, the first current is controlled on the basis of an inclination angle between the liquid surface and the film-formation surface.Type: ApplicationFiled: March 9, 2011Publication date: June 30, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Akira FURUYA, Yasuaki TSUCHIYA
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Patent number: 7955980Abstract: A post-CMP cleaning process of a copper layer is to be performed as follows. An alkaline aqueous solution, a polycarboxylic acid, BTA, and an alkaline aqueous solution are sequentially brought into contact with a primary surface of a silicon substrate over which the copper layer is provided.Type: GrantFiled: August 18, 2009Date of Patent: June 7, 2011Assignee: Renesas Electronics CorporationInventors: Toshiyuki Takewaki, Manabu Iguchi, Daisuke Oshida, Hironori Toyoshima, Masayuki Hiroi, Takuji Onuma, Hiroaki Nanba, Ichiro Honma, Mieko Hasegawa, Yasuaki Tsuchiya, Toshiji Taiji, Takaharu Kunugi
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Publication number: 20090305496Abstract: A post-CMP cleaning process of a copper layer is to be performed as follows. An alkaline aqueous solution, a polycarboxylic acid, BTA, and an alkaline aqueous solution are sequentially brought into contact with a primary surface of a silicon substrate over which the copper layer is provided.Type: ApplicationFiled: August 18, 2009Publication date: December 10, 2009Applicant: NEC ELECTRONICS CORPORATIONInventors: Toshiyuki TAKEWAKI, Manabu IGUCHI, Daisuke OSHIDA, Hironori TOYOSHIMA, Masayuki HIROI, Takuji ONUMA, Hiroaki NANBA, Ichiro HONMA, Mieko HASEGAWA, Yasuaki TSUCHIYA, Toshiji TAIJI, Takaharu KUNUGI
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Patent number: 7601640Abstract: A post-CMP cleaning process of a copper layer is to be performed as follows. An alkaline aqueous solution, a polycarboxylic acid, BTA, and an alkaline aqueous solution are sequentially brought into contact with a primary surface of a silicon substrate over which the copper layer is provided.Type: GrantFiled: December 10, 2007Date of Patent: October 13, 2009Assignee: NEC Electronics CorporationInventors: Toshiyuki Takewaki, Manabu Iguchi, Daisuke Oshida, Hironori Toyoshima, Masayuki Hiroi, Takuji Onuma, Hiroaki Nanba, Ichiro Honma, Mieko Hasegawa, Yasuaki Tsuchiya, Toshiji Taiji, Takaharu Kunugi
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Publication number: 20080160750Abstract: A post-CMP cleaning process of a copper layer is to be performed as follows. An alkaline aqueous solution, a polycarboxylic acid, BTA, and an alkaline aqueous solution are sequentially brought into contact with a primary surface of a silicon substrate over which the copper layer is provided.Type: ApplicationFiled: December 10, 2007Publication date: July 3, 2008Applicant: NEC ELECTRONICS CORPORATIONInventors: Toshiyuki TAKEWAKI, Manabu Iguchi, Daisuke Oshida, Hironori Toyoshima, Masayuki Hiroi, Takuji Onuma, Hiroaki Nanba, Ichiro Honma, Mieko Hasegawa, Yasuaki Tsuchiya, Toshiji Taiji, Takahara Kunugi
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Patent number: 7229570Abstract: The present invention relates to a slurry for chemical mechanical polishing, which contains a silica polishing material, an oxidizing agent, a benzotriazole-based compound, a diketone and water.Type: GrantFiled: July 11, 2003Date of Patent: June 12, 2007Assignee: NEC Electronics CorporationInventors: Toshiji Taiji, Yasuaki Tsuchiya, Tomoyuki Ito, Kenichi Aoyagi, Shin Sakurai
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Publication number: 20060237319Abstract: An objective of this invention is to reliably form a plating film. The following two steps are sequentially conducted: step 101 of connecting a film-formation surface of a wafer 109 to a cathode electrode 107, making the film-formation surface inclined from the surface of a plating solution 103 and immersing the wafer 109 into the plating solution 103 with applying a first current between the cathode electrode 107 and an Cu anode electrode 105 disposed in the plating solution 103, and step 103 of, after immersing the film-formation surface in the plating solution 103, applying a second current between the cathode electrode 107 and the Cu anode electrode 105 to form a metal film on the film-formation surface by electrolytic plating. In step 101, the first current is controlled on the basis of an inclination angle between the liquid surface and the film-formation surface.Type: ApplicationFiled: April 21, 2006Publication date: October 26, 2006Inventors: Akira Furuya, Yasuaki Tsuchiya
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Patent number: 7091123Abstract: In a method of forming a metal wiring line, a first insulating film is formed directly or indirectly on a semiconductor substrate. A second insulating film is formed on the first insulating film. A wiring line groove is formed to pass through the second insulating film to an inside of the first insulating film. A conductive film is formed to fill the wiring line groove and to cover the second insulating film. The conductive film and the second insulating film are removed by a first CMP polishing process, using the first insulating film as a stopper film, until the first insulating film is exposed.Type: GrantFiled: August 30, 2002Date of Patent: August 15, 2006Assignee: NEC Electronics CorporationInventors: Takashi Tonegawa, Yasuaki Tsuchiya, Tomoko Inoue
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Patent number: 7067427Abstract: A method of manufacturing a semiconductor device includes the steps of forming a sunken section in an insulating film formed on a substrate and forming a barrier metal film on the insulating film inclusive of the sunken section. The method also includes forming a copper-based film over the entire surface so as to fill up the sunken section and forming a copper-based metal interconnection. The interconnection is formed by polishing this substrate surface by the chemical mechanical polishing method, using a polishing slurry containing a silica polishing material, an oxidizing agent, an amino acid, a triazole-based compound and water. A content ratio of the amino acid to the triazole-based compound (amino acid/triazole-based compound (weight ratio)) is 5 to 8.Type: GrantFiled: July 15, 2003Date of Patent: June 27, 2006Assignee: NEC Electronics CorporationInventors: Yasuaki Tsuchiya, Tomoko Inoue