Patents by Inventor Yasuchika OKIZUMI

Yasuchika OKIZUMI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10381373
    Abstract: A method of forming a three-dimensional memory device includes forming at the least one lower level dielectric layer over a semiconductor substrate, forming a buried source line over the least one lower level dielectric layer and over the semiconductor substrate, such that the buried source line is electrically connected to the semiconductor substrate, forming an alternating stack of insulating layers and sacrificial material layers over the buried source line, such that the sacrificial material layers are subsequently replaced with, electrically conductive layers, forming memory openings through the alternating stack by etching through the alternating stack after the buried source line is electrically connected to the semiconductor substrate, and forming memory stack structures in the memory openings. Each memory stack structure includes a vertical semiconductor channel electrically connected to the buried source line and a memory film laterally surrounding the vertical semiconductor channel.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: August 13, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yasuchika Okizumi, Michiru Hirayama, Naoto Norizuki, Satoshi Shimizu, Yasuo Kasagi, Kimiaki Naruse
  • Patent number: 10192877
    Abstract: A mesa structure is formed over a substrate. An alternating stack of insulating layers and spacer material layers having a total height of approximately double the height of the mesa structure is formed over the substrate and the mesa structure. The spacer material layers are formed as, or are replaced with, electrically conductive layers. Portions of the alternating stack are removed from above the mesa structure by a planarization process. Stepped surfaces can be concurrently formed in a first terrace region overlying the mesa structure and in a second terrace region located at an opposite side of a memory array region of the alternating stack. A pair of level shifted stepped surfaces is formed. Contacts to the alternating stack can reach down only to the lowest surface of the pair of level shifted stepped surfaces, and can be shorter than the alternating stack.
    Type: Grant
    Filed: March 7, 2017
    Date of Patent: January 29, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Naoto Norizuki, Yasuchika Okizumi, Shogo Mada, Hiroyuki Ogawa
  • Publication number: 20180366487
    Abstract: A method of forming a three-dimensional memory device includes forming at the least one lower level dielectric layer over a semiconductor substrate, forming a buried source line over the least one lower level dielectric layer and over the semiconductor substrate, such that the buried source line is electrically connected to the semiconductor substrate, forming an alternating stack of insulating layers and sacrificial material layers over the buried source line, such that the sacrificial material layers are subsequently replaced with, electrically conductive layers, forming memory openings through the alternating stack by etching through the alternating stack after the buried source line is electrically connected to the semiconductor substrate, and forming memory stack structures in the memory openings. Each memory stack structure includes a vertical semiconductor channel electrically connected to the buried source line and a memory film laterally surrounding the vertical semiconductor channel.
    Type: Application
    Filed: September 29, 2017
    Publication date: December 20, 2018
    Inventors: Yasuchika Okizumi, Michiru Hirayama, Naoto Norizuki, Satoshi Shimizu, Yasuo Kasagi, Kimiaki Naruse
  • Publication number: 20180261611
    Abstract: A mesa structure is formed over a substrate. An alternating stack of insulating layers and spacer material layers having a total height of approximately double the height of the mesa structure is formed over the substrate and the mesa structure. The spacer material layers are formed as, or are replaced with, electrically conductive layers. Portions of the alternating stack are removed from above the mesa structure by a planarization process. Stepped surfaces can be concurrently formed in a first terrace region overlying the mesa structure and in a second terrace region located at an opposite side of a memory array region of the alternating stack. A pair of level shifted stepped surfaces is formed. Contacts to the alternating stack can reach down only to the lowest surface of the pair of level shifted stepped surfaces, and can be shorter than the alternating stack.
    Type: Application
    Filed: March 7, 2017
    Publication date: September 13, 2018
    Inventors: Naoto NORIZUKI, Yasuchika OKIZUMI, Shogo MADA, Hiroyuki OGAWA