Abstract: It is intended to improve reading speed of pixel signals in a solid-state imaging element provided with an ADC. A plurality of pixels are arrayed in a pixel block. A drive circuit drives the pixel block to output a plurality of pixel signals at the same time. A comparator successively selects the plurality of pixel signals and compares the selected pixel signals and a predetermined reference signal. A control section generates a control signal for updating the predetermined reference signal on the basis of comparison results of the comparator. A reference signal update section updates the predetermined reference signal according to the control signal.

Abstract: It is intended to improve reading speed of pixel signals in a solid-state imaging element provided with an ADC. A plurality of pixels are arrayed in a pixel block. A drive circuit drives the pixel block to output a plurality of pixel signals at the same time. A comparator successively selects the plurality of pixel signals and compares the selected pixel signals and a predetermined reference signal. A control section generates a control signal for updating the predetermined reference signal on the basis of comparison results of the comparator. A reference signal update section updates the predetermined reference signal according to the control signal.

Abstract: It is intended to improve reading speed of pixel signals in a solid-state imaging element provided with an ADC. A plurality of pixels are arrayed in a pixel block. A drive circuit drives the pixel block to output a plurality of pixel signals at the same time. A comparator successively selects the plurality of pixel signals and compares the selected pixel signals and a predetermined reference signal. A control section generates a control signal for updating the predetermined reference signal on the basis of comparison results of the comparator. A reference signal update section updates the predetermined reference signal according to the control signal.

Abstract: Solid-state imaging devices and electronic equipment are disclosed. In one example, a solid-state imaging device includes a pixel array section with pixels that perform photoelectric conversion disposed in an array. A preamplifier section receives pixel signals from the pixels and a threshold signal, and amplifies their differences as differential signals. The preamplifier section is set to a shutdown state on the basis of a first control signal input. A comparator compares the differential signals with a comparison reference signal. A preamplifier through circuit includes switching elements connecting the input terminals of the preamplifier section to input terminals of the comparator section, and sets the switching elements to a connection state on the basis of a second control signal input in the shutdown state. Thus, power consumption can be reduced under conditions that allow characteristics required for the preamplifier section to be moderated.

Abstract: An A/D converter and electronic equipment are disclosed. In one example, an A/D converter includes a comparator circuit and a first transistor. The comparator circuit compares a threshold voltage (Vth) to a pixel signal (SVSL). The first transistor has a control terminal and forms a clamp circuit, and receives an input of a result of the comparison. When the clamp circuit is turned on (closed), the first transistor equalizes currents flowing to a first predetermined position and a second predetermined position or equalizes voltages at the first predetermined position and the second predetermined position, the first predetermined position and the second predetermined position being connected to each other at the time of clamping. This makes it possible to suppress occurrence of streaking in a case where an excessive input is applied to a pixel signal line side.

Abstract: Solid-state imaging devices and electronic equipment are disclosed. In one example, a solid-state imaging device includes a pixel array section with pixels that perform photoelectric conversion disposed in an array. A preamplifier section receives pixel signals from the pixels and a threshold signal, and amplifies their differences as differential signals. The preamplifier section is set to a shutdown state on the basis of a first control signal input. A comparator compares the differential signals with a comparison reference signal. A preamplifier through circuit includes switching elements connecting the input terminals of the preamplifier section to input terminals of the comparator section, and sets the switching elements to a connection state on the basis of a second control signal input in the shutdown state. Thus, power consumption can be reduced under conditions that allow characteristics required for the preamplifier section to be moderated.

Abstract: An A/D converter and electronic equipment are disclosed. In one example, an A/D converter includes a comparator circuit and a first transistor. The comparator circuit compares a threshold voltage (Vth) to a pixel signal (SVSL). The first transistor has a control terminal and forms a clamp circuit, and receives an input of a result of the comparison. When the clamp circuit is turned on (closed), the first transistor equalizes currents flowing to a first predetermined position and a second predetermined position or equalizes voltages at the first predetermined position and the second predetermined position, the first predetermined position and the second predetermined position being connected to each other at the time of clamping. This makes it possible to suppress occurrence of streaking in a case where an excessive input is applied to a pixel signal line side.

Abstract: It is intended to improve reading speed of pixel signals in a solid-state imaging element provided with an ADC. A plurality of pixels are arrayed in a pixel block. A drive circuit drives the pixel block to output a plurality of pixel signals at the same time. A comparator successively selects the plurality of pixel signals and compares the selected pixel signals and a predetermined reference signal. A control section generates a control signal for updating the predetermined reference signal on the basis of comparison results of the comparator. A reference signal update section updates the predetermined reference signal according to the control signal.

Abstract: There is provided a signal transmission device including reception processing units for respective channels, so as to enable multichannel transmission by dividing frequency bands. The total number of channels is equal to or greater than three. When full-duplex two-way communication is applied in any combination of two channels, one of reception processing unit include a signal suppressing unit configured to suppress a signal component of a channel other than a self channel.

Abstract: A signal output circuit includes: an output buffer including a first terminal configured to output a first output signal; a first output terminal; a first switch inserted on a signal path from the first terminal to the first output terminal; and a second switch configured to transmit a predetermined voltage to the first output terminal when being turned on.

Abstract: There is provided a signal transmission device including reception processing units for respective channels, so as to enable multichannel transmission by dividing frequency bands. The total number of channels is equal to or greater than three. When full-duplex two-way communication is applied in any combination of two channels, one of reception processing unit include a signal suppressing unit configured to suppress a signal component of a channel other than a self channel.

Abstract: A D/A converter includes: an (N?1)-stage reference resistor group; an N-stage reference resistor group; inter-stage op-amps applying a divided voltage outputted from voltage taps of the (N?1)-stage reference resistor group, across both ends of the N-stage reference resistor group as the Nth reference voltage; a dynamic range expanding means for arranging the voltage taps in the (N?1)-stage reference resistor group so as to expand upward and downward, to expand an input dynamic range in the N-stage reference resistor group; and expansion resistors arranged respectively at both upper and lower ends of the N-stage reference resistor group in response to upward and downward expanded amounts of the dynamic range.

Abstract: A D/A converter includes: an (N?1)-stage reference resistor group; an N-stage reference resistor group; inter-stage op-amps applying a divided voltage outputted from voltage taps of the (N?1)-stage reference resistor group, across both ends of the N-stage reference resistor group as the Nth reference voltage; a dynamic range expanding means for arranging the voltage taps in the (N?1)-stage reference resistor group so as to expand upward and downward, to expand an input dynamic range in the N-stage reference resistor group; and expansion resistors arranged respectively at both upper and lower ends of the N-stage reference resistor group in response to upward and downward expanded amounts of the dynamic range.